Year |
Citation |
Score |
2020 |
Jindal N, Gupta S, Ravipati DP, Panda PR, Sarangi SR. Enhancing Network-on-Chip Performance by Reusing Trace Buffers Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 39: 922-935. DOI: 10.1109/Tcad.2019.2907909 |
0.315 |
|
2020 |
Moolchandani D, Kumar A, Sarangi SR. Accelerating CNN Inference on ASICs: A survey Journal of Systems Architecture. 101887. DOI: 10.1016/J.Sysarc.2020.101887 |
0.331 |
|
2019 |
Sultan H, Chauhan A, Sarangi SR. A Survey of Chip-level Thermal Simulators Acm Computing Surveys. 52: 42. DOI: 10.1145/3309544 |
0.338 |
|
2019 |
Bashir J, Peter E, Sarangi SR. BigBus: A Scalable Optical Interconnect Acm Journal On Emerging Technologies in Computing Systems. 15: 1-24. DOI: 10.1145/3289391 |
0.305 |
|
2018 |
Ananthanarayanan G, Sarangi SR, Balakrishnan M. Task Assignment Algorithms for Multicore Platforms with Process Variations Journal of Low Power Electronics. 14: 302-317. DOI: 10.1166/Jolpe.2018.1550 |
0.324 |
|
2018 |
Kalayappan R, Sarangi SR. Providing Accountability in Heterogeneous Systems-on-Chip Acm Transactions in Embedded Computing Systems. 17: 83. DOI: 10.1145/3241048 |
0.359 |
|
2018 |
Jindal N, Panda PR, Sarangi SR. Reusing Trace Buffers as Victim Caches Ieee Transactions On Very Large Scale Integration Systems. 26: 1699-1712. DOI: 10.1109/Tvlsi.2018.2827928 |
0.422 |
|
2017 |
Chandran S, Panda PR, Sarangi SR, Bhattacharyya A, Chauhan D, Kumar S. Managing Trace Summaries to Minimize Stalls During Postsilicon Validation Ieee Transactions On Very Large Scale Integration Systems. 25: 1881-1894. DOI: 10.1109/Tvlsi.2017.2657604 |
0.347 |
|
2016 |
Aggarwal P, Sarangi SR. Lock-Free and Wait-Free Slot Scheduling Algorithms Ieee Transactions On Parallel and Distributed Systems. 27: 1387-1400. DOI: 10.1109/Tpds.2015.2435786 |
0.307 |
|
2015 |
Kalayappan R, Sarangi SR. FluidCheck: A redundant threading-based approach for reliable execution in manycore processors Acm Transactions On Architecture and Code Optimization. 12. DOI: 10.1145/2842620 |
0.454 |
|
2015 |
Chandran S, Sarangi SR, Panda PR. Area-Aware Cache Update Trackers for Postsilicon Validation Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. DOI: 10.1109/Tvlsi.2015.2480378 |
0.341 |
|
2015 |
Arora A, Harne M, Sultan H, Bagaria A, Sarangi SR. FP-NUCA: A Fast NOC Layer for Implementing Large NUCA Caches Ieee Transactions On Parallel and Distributed Systems. 26: 2465-2478. DOI: 10.1109/Tpds.2014.2358231 |
0.376 |
|
2014 |
Sultan H, Ananthanarayanan G, Sarangi SR. Processor power estimation techniques: A survey International Journal of High Performance Systems Architecture. 5: 93-114. DOI: 10.1504/Ijhpsa.2014.061448 |
0.35 |
|
2014 |
Malhotra G, Aggarwal P, Sagar A, Sarangi SR. ParTejas: A parallel simulator for multicore processors Ispass 2014 - Ieee International Symposium On Performance Analysis of Systems and Software. 130-131. DOI: 10.1145/3077582 |
0.33 |
|
2014 |
Peter E, Arora A, Bagaria A, Sarangi SR. Optical overlay NUCA: A high speed substrate for shared L2 caches 2014 21st International Conference On High Performance Computing, Hipc 2014. DOI: 10.1145/3064833 |
0.324 |
|
2014 |
Chandran S, Kallurkar P, Gupta P, Sarangi SR. Architectural support for handling jitterin shared memory based parallel applications Ieee Transactions On Parallel and Distributed Systems. 25: 1166-1176. DOI: 10.1109/Tpds.2013.127 |
0.361 |
|
2013 |
Ananthanarayanan G, Malhotra G, Balakrishnan M, Sarangi SR. Amdahl's law in the era of process variation International Journal of High Performance Systems Architecture. 4: 218-230. DOI: 10.1504/Ijhpsa.2013.058984 |
0.444 |
|
2013 |
Kalayappan R, Sarangi SR. A survey of checker architectures Acm Computing Surveys. 45. DOI: 10.1145/2501654.2501662 |
0.335 |
|
2012 |
Sarangi SR, Dutta P, Jalan K. IT infrastructure for providing energy-as-a-service to electric vehicles Ieee Transactions On Smart Grid. 3: 594-604. DOI: 10.1109/Tsg.2011.2175953 |
0.329 |
|
2008 |
Sarangi SR, Greskamp B, Teodorescu R, Nakano J, Tiwari A, Torrellas J. VARIUS: A model of process variation and resulting timing errors for microarchitects Ieee Transactions On Semiconductor Manufacturing. 21: 3-13. DOI: 10.1109/Tsm.2007.913186 |
0.479 |
|
2007 |
Tiwari A, Sarangi SR, Torrellas J. ReCycle: Pipeline adaptation to tolerate process variation Proceedings - International Symposium On Computer Architecture. 323-334. DOI: 10.1145/1250662.1250703 |
0.533 |
|
2007 |
Sarangi S, Narayanasamy S, Carneal B, Tiwari A, Calder B, Torrellas J. Patching processor design errors with programmable hardware Ieee Micro. 27: 12-25. DOI: 10.1109/Mm.2007.19 |
0.622 |
|
2007 |
Sarangi SR, Greskamp B, Torrellas J. A model for timing errors in processors with parameter variation Proceedings - Eighth International Symposium On Quality Electronic Design, Isqed 2007. 647-654. DOI: 10.1109/ISQED.2007.16 |
0.671 |
|
2007 |
Greskamp B, Sarangi SR, Torrellas J. Threshold voltage variation effects on aging-related hard failure rates Proceedings - Ieee International Symposium On Circuits and Systems. 1261-1264. |
0.566 |
|
2006 |
Renau J, Strauss K, Ceze L, Liu W, Sarangi SR, Tuck J, Torrellas J. Energy-efficient thread-level speculation Ieee Micro. 26: 80-91. DOI: 10.1109/Mm.2006.11 |
0.641 |
|
2006 |
Sarangi SR, Tiwari A, Torrellas J. Phoenix: detecting and recovering from permanent processor design bugs with programmable hardware Proceedings of the Annual International Symposium On Microarchitecture, Micro. 26-37. DOI: 10.1109/MICRO.2006.41 |
0.539 |
|
2006 |
Sarangi SR, Greskamp B, Torrellas J. CADRE: Cycle-accurate deterministic replay for hardware debugging Proceedings of the International Conference On Dependable Systems and Networks. 2006: 301-310. DOI: 10.1109/DSN.2006.19 |
0.572 |
|
2005 |
Sarangi SR, Liu W, Torrellas J, Zhou Y. ReSlice: Selective re-execution of long-retired misspeculated instructions using forward slicing Proceedings of the Annual International Symposium On Microarchitecture, Micro. 257-268. DOI: 10.1109/MICRO.2005.28 |
0.565 |
|
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