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Lawrence T. Clark - Publications

Affiliations: 
Electrical Engineering Arizona State University, Tempe, AZ, United States 
Area:
Electronics and Electrical Engineering, Design and Decorative Arts
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104 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2019 Brunhaver J, Uhrie R, Clark LT. Itemization and Track Limitations of Fan-Out-Free Functions for Static CMOS Functional Cells Ieee Transactions On Circuits and Systems Ii-Express Briefs. 66: 1164-1168. DOI: 10.1109/Tcsii.2018.2875334  0.346
2019 Clark LT, Medapuram SB, Kadiyala DK, Brunhaver J. Physically Unclonable Functions Using Foundry SRAM Cells Ieee Transactions On Circuits and Systems I-Regular Papers. 66: 955-966. DOI: 10.1109/Tcsi.2018.2873777  0.461
2019 Clark LT, Adams J, Holbert KE. Reliable techniques for integrated circuit identification and true random number generation using 1.5-transistor flash memory Integration. 65: 263-272. DOI: 10.1016/J.Vlsi.2017.10.001  0.441
2018 Clark LT, Medapuram SB, Kadiyala DK. SRAM Circuits for True Random Number Generation Using Intrinsic Bit Instability Ieee Transactions On Very Large Scale Integration Systems. 26: 2027-2037. DOI: 10.1109/Tvlsi.2018.2840049  0.483
2017 Vashishtha V, Masand L, Dosi A, Ramamurthy C, Clark LT. Systematic analysis of the timing and power impact of pure lines and cuts routing for multiple patterning Proceedings of Spie. 10148. DOI: 10.1117/12.2258085  0.374
2016 Chellappa S, Clark LT. SRAM-based unique chip identifier techniques Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 24: 1213-1222. DOI: 10.1109/Tvlsi.2015.2445751  0.491
2016 Farnsworth C, Clark LT, Gogulamudi AR, Vashishtha V, Gujja A. A Soft-Error Mitigated Microprocessor with Software Controlled Error Reporting and Recovery Ieee Transactions On Nuclear Science. 63: 2241-2249. DOI: 10.1109/Tns.2016.2540619  0.353
2016 Saremi M, Privat A, Barnaby HJ, Clark LT. Physically Based Predictive Model for Single Event Transients in CMOS Gates Ieee Transactions On Electron Devices. DOI: 10.1109/Ted.2016.2547423  0.329
2016 Clark LT, Patterson DW, Ramamurthy C, Holbert KE. An embedded microprocessor radiation hardened by microarchitecture and circuits Ieee Transactions On Computers. 65: 382-395. DOI: 10.1109/Tc.2015.2419661  0.542
2016 Clark LT, Vashishtha V, Shifren L, Gujja A, Sinha S, Cline B, Ramamurthy C, Yeric G. ASAP7: A 7-nm finFET predictive process design kit Microelectronics Journal. 53: 105-115. DOI: 10.1016/J.Mejo.2016.04.006  0.397
2015 Ramamurthy C, Chellappa S, Vashishtha V, Gogulamudi A, Clark LT. High Performance Low Power Pulse-Clocked TMR Circuits for Soft-Error Hardness Ieee Transactions On Nuclear Science. 62: 3040-3048. DOI: 10.1109/Tns.2015.2498919  0.477
2015 Clark LT, Holbert KE, Adams JW, Navale H, Anderson BC. Evaluation of 1.5-T Cell Flash Memory Total Ionizing Dose Response Ieee Transactions On Nuclear Science. 62: 2431-2439. DOI: 10.1109/Tns.2015.2488539  0.391
2015 Shambhulingaiah S, Lieb C, Clark LT. Circuit Simulation Based Validation of Flip-Flop Robustness to Multiple Node Charge Collection Ieee Transactions On Nuclear Science. DOI: 10.1109/Tns.2015.2453795  0.46
2015 De La Rosa JM, Chiang P, Clark LT. Guest Editorial: Special Section on the 2014 IEEE Custom Integrated Circuits Conference (CICC 2014) Ieee Transactions On Circuits and Systems I: Regular Papers. 62: 1897-1898. DOI: 10.1109/Tcsi.2015.2458411  0.368
2015 Gujja A, Chellappa S, Ramamurthy C, Clark LT. Redundant skewed clocking of pulse-clocked latches for low power soft error mitigation Proceedings of the European Conference On Radiation and Its Effects On Components and Systems, Radecs. 2015. DOI: 10.1109/RADECS.2015.7365658  0.323
2015 Ramamurthy C, Chellappa S, Clark LT. Physical design methodologies for soft error mitigation using redundancy Proceedings of the European Conference On Radiation and Its Effects On Components and Systems, Radecs. 2015. DOI: 10.1109/RADECS.2015.7365647  0.324
2015 Gogulamudi AR, Clark LT, Farnsworth C, Chellappa S, Vashishtha V. Architectural and micro-architectural techniques for software controlled microprocessor soft-error mitigation Proceedings of the European Conference On Radiation and Its Effects On Components and Systems, Radecs. 2015. DOI: 10.1109/RADECS.2015.7365588  0.344
2015 Chellappa S, Ramamurthy C, Vashishtha V, Clark LT. Advanced encryption system with dynamic pipeline reconfiguration for minimum energy operation Proceedings - International Symposium On Quality Electronic Design, Isqed. 2015: 201-206. DOI: 10.1109/ISQED.2015.7085425  0.339
2015 Vashishtha V, Gujja A, Clark LT. Delay and power tradeoffs for static and dynamic register files Proceedings - Ieee International Symposium On Circuits and Systems. 2015: 2900-2903. DOI: 10.1109/ISCAS.2015.7169293  0.383
2015 Kumar S, Chellappa S, Clark LT. Temporal pulse-clocked multi-bit flip-flop mitigating SET and SEU Proceedings - Ieee International Symposium On Circuits and Systems. 2015: 814-817. DOI: 10.1109/ISCAS.2015.7168758  0.308
2015 Vashishtha V, Clark LT, Chellappa S, Gogulamudi AR, Gujja A, Farnsworth C. A soft-error hardened process portable embedded microprocessor Proceedings of the Custom Integrated Circuits Conference. 2015. DOI: 10.1109/CICC.2015.7338366  0.381
2014 Clark LT, Shambhulingaiah S. Methodical design approaches to radiation effects analysis and mitigation in flip-flop circuits Proceedings of Ieee Computer Society Annual Symposium On Vlsi, Isvlsi. 595-600. DOI: 10.1109/ISVLSI.2014.74  0.367
2013 Mhambrey SS, Maurya SK, Clark LT. Low complexity out-of-order issue logic using static circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 21: 380-384. DOI: 10.1109/TVLSI.2012.2184310  0.368
2013 Rogenmoser R, Clark LT. Reducing transistor variability for high performance low power chips Ieee Micro. 33: 18-26. DOI: 10.1109/Mm.2013.10  0.465
2013 Clark LT, Leshner S, Tien G. SRAM cell optimization for low AVT transistors Proceedings of the International Symposium On Low Power Electronics and Design. 57-63. DOI: 10.1109/ISLPED.2013.6629267  0.319
2012 Chellappa S, Clark LT, Holbert KE. A 90-nm radiation hardened clock spine Ieee Transactions On Nuclear Science. 59: 1020-1026. DOI: 10.1109/TNS.2012.2183647  0.379
2011 Maurya SK, Clark LT. A specialized static content addressable memory for longest prefix matching in internet protocol routing Journal of Low Power Electronics. 7: 350-363. DOI: 10.1166/Jolpe.2011.1142  0.66
2011 Maurya SK, Clark LT. A dynamic longest prefix matching content addressable memory for IP routing Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 19: 963-972. DOI: 10.1109/Tvlsi.2010.2042826  0.617
2011 Hindman ND, Clark LT, Patterson DW, Holbert KE. Fully automated, testable design of fine-grained triple mode redundant logic Ieee Transactions On Nuclear Science. 58: 3046-3052. DOI: 10.1109/Tns.2011.2169280  0.651
2011 Clark LT, Patterson DW, Hindman ND, Holbert KE, Maurya S, Guertin SM. A dual mode redundant approach for microprocessor soft error hardness Ieee Transactions On Nuclear Science. 58: 3018-3025. DOI: 10.1109/Tns.2011.2168828  0.662
2011 Lee EH, Indluru A, Allee DR, Clark LT, Holbert KE, Alford TL. Effects of gamma irradiation and electrical stress on a-Si:H thin-film transistors for flexible electronics and displays Ieee/Osa Journal of Display Technology. 7: 325-329. DOI: 10.1109/Jdt.2011.2113314  0.345
2011 Clark LT, Pettit DE, Holbert KE, Hindman ND. Validation of and delay variation in total ionizing dose hardened standard cell libraries Proceedings - Ieee International Symposium On Circuits and Systems. 2051-2054. DOI: 10.1109/ISCAS.2011.5938000  0.595
2011 Clark LT, Chen TH, Chaudhary V. Efficient voltage conversion for SRAM low standby power modes Proceedings - Ieee International Symposium On Circuits and Systems. 73-76. DOI: 10.1109/ISCAS.2011.5937504  0.354
2011 Chellappa S, Dey A, Clark LT. Improved circuits for microchip identification using SRAM mismatch Proceedings of the Custom Integrated Circuits Conference. DOI: 10.1109/CICC.2011.6055318  0.395
2011 Wang X, Holbert KE, Clark LT. Single event upset mitigation techniques for FPGAs utilized in nuclear power plant digital instrumentation and control Nuclear Engineering and Design. 241: 3317-3324. DOI: 10.1016/J.Nucengdes.2011.06.033  0.493
2010 Darbanian N, Venugopal SM, Gopalan SG, Allee DR, Clark LT. Flexible amorphous-silicon non-volatile memory Journal of the Society For Information Display. 18: 346-350. DOI: 10.1889/Jsid18.5.346  0.442
2010 Mhambrey SS, Clark LT, Maurya SK, Berezowski KS. Out-of-order issue logic using sorting networks Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 385-388. DOI: 10.1145/1785481.1785570  0.35
2010 Sengupta R, Vermeire B, Clark LT, Bakkaloglu B. A 133 MHz radiation-hardened delay-locked loop Ieee Transactions On Nuclear Science. 57: 3626-3633. DOI: 10.1109/Tns.2010.2086485  0.485
2010 Matush BI, Mozdzen TJ, Clark LT, Knudsen JE. Area-efficient temporally hardened by design flip-flop circuits Ieee Transactions On Nuclear Science. 57: 3588-3595. DOI: 10.1109/Tns.2010.2077311  0.437
2010 Yao X, Clark LT, Chellappa S, Holbert KE, Hindman ND. Design and experimental validation of radiation hardened by design SRAM cells Ieee Transactions On Nuclear Science. 57: 258-265. DOI: 10.1109/Tns.2009.2034661  0.637
2010 Maurya SK, Clark LT. Fast and scalable priority encoding using static CMOS Iscas 2010 - 2010 Ieee International Symposium On Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 433-436. DOI: 10.1109/ISCAS.2010.5537688  0.623
2010 Yao X, Clark LT, Patterson DW, Holbert KE. Single event transient mitigation in cache memory using transient error checking circuits Proceedings of the Custom Integrated Circuits Conference. DOI: 10.1109/CICC.2010.5617439  0.393
2010 Puri R, Holbert KE, Clark LT. Soft error reduction in FPGAs for digital I&C in nuclear power plants International Congress On Advances in Nuclear Power Plants 2010, Icapp 2010. 2: 808-816.  0.356
2010 Wang X, Holbert KE, Clark LT. Using TMR to mitigate SEUs for digital instrumentation and control in nuclear power plants 7th International Topical Meeting On Nuclear Plant Instrumentation, Control, and Human-Machine Interface Technologies 2010, Npic and Hmit 2010. 2: 925-934.  0.381
2009 Maurya SK, Clark LT. Low power fast and dense longest prefix match content addressable memory for IP routers Proceedings of the International Symposium On Low Power Electronics and Design. 389-394. DOI: 10.1145/1594233.1594333  0.623
2009 Clark LT, Nielsen KE, Holbert KE. Radiation hardened by design digital I/O for high SEE and TID immunity Ieee Transactions On Nuclear Science. 56: 3408-3414. DOI: 10.1109/Tns.2009.2034376  0.396
2009 Allee DR, Clark LT, Vogt BD, Shringarpure R, Venugopal SM, Uppili SG, Kaftanoglu K, Shivalingaiah H, Li ZP, Fernando JJR, Bawolek EJ, O'Rourke SM. Circuit-level impact of a-Si:H thin-film-transistor degradation effects Ieee Transactions On Electron Devices. 56: 1166-1176. DOI: 10.1109/Ted.2009.2019387  0.369
2009 Yao X, Clark LT, Patterson DW, Holbert KE. A 90 nm bulk CMOS radiation hardened by design cache memory Proceedings of the European Conference On Radiation and Its Effects On Components and Systems, Radecs. 473-480. DOI: 10.1109/RADECS.2009.5994698  0.374
2009 Clark LT, Chan Carusone A, Heydari P. Introduction to the Special Issue on the 2008 IEEE Custom Integrated Circuits Conference Ieee Journal of Solid-State Circuits. 44: 2083-2084. DOI: 10.1109/Jssc.2009.2028056  0.458
2009 Samson G, Clark LT. Low-power race-free programmable logic arrays Ieee Journal of Solid-State Circuits. 44: 935-946. DOI: 10.1109/JSSC.2009.2013764  0.445
2009 Uppili SG, Allee DR, Venugopal SM, Clark LT, Shringarpure R. Standard cell library and automated design flow for circuits on flexible substrates 2009 Flexible Electronics and Displays Conference and Exhibition, Flex 2009. DOI: 10.1109/FEDC.2009.5069270  0.36
2009 Desai NN, Haigh JR, Clark LT. Reducing process variation impact on replica-timed static random access memory sense timing Integration, the Vlsi Journal. 42: 437-448. DOI: 10.1016/J.Vlsi.2009.03.002  0.46
2008 Badrudduza SA, Wang Z, Samson G, Clark LT. Leakage controlled read stable static random access memories Journal of Computers. 3: 39-49. DOI: 10.4304/Jcp.3.4.39-49  0.53
2008 Shringarpure R, Venugopal S, Kaftanoglu K, Clark LT, Allee DR, Bawolek E. Compact modeling of amorphous-silicon thin-film transistors with BSIM3 Journal of the Society For Information Display. 16: 1147-1155. DOI: 10.1889/Jsid16.11.1147  0.326
2008 Yao X, Hindman N, Clark LT, Holbert KE, Alexander DR, Shedd WM. The impact of total ionizing dose on unhardened SRAM cell margins Ieee Transactions On Nuclear Science. 55: 3280-3287. DOI: 10.1109/Tns.2008.2007122  0.627
2008 Allee DR, Clark LT, Shringarpure R, Venugopal SM, Li ZP, Bawolek EJ. Degradation effects in a-si:h thin film transistors and their impact on circuit performance Ieee International Reliability Physics Symposium Proceedings. 158-167. DOI: 10.1109/RELPHY.2008.4558878  0.308
2008 Chen TH, Clark LT, Holbert KE. Memory design for high temperature radiation environments Ieee International Reliability Physics Symposium Proceedings. 107-114. DOI: 10.1109/RELPHY.2008.4558870  0.368
2008 Shringarpure R, Venugopal S, Clark LT, Allee DR, Bawolek E. Localization of gate bias induced threshold voltage degradation in a-Si:H TFTs Ieee Electron Device Letters. 29: 93-95. DOI: 10.1109/Led.2007.911609  0.347
2008 Clark LT, Gharpurey R, Heydari P. Introduction to the special issue on the IEEE 2007 custom integrated circuits conference Ieee Journal of Solid-State Circuits. 43: 1714-1716. DOI: 10.1109/JSSC.2008.925600  0.379
2008 Samson G, Ananthapadmanabhan N, Badrudduza SA, Clark LT. Low-power dynamic memory word line decoding for static random access memories Ieee Journal of Solid-State Circuits. 43: 2524-2532. DOI: 10.1109/Jssc.2008.2005813  0.468
2008 Shringarpure R, Clark LT, Venugopal SM, Allee DR, Uppili SG. Amorphous silicon logic circuits on flexible substrates Proceedings of the Custom Integrated Circuits Conference. 181-184. DOI: 10.1109/CICC.2008.4672053  0.35
2008 Clark LT, Kabir M, Knudsen JE. A low standby power flip-flop with reduced circuit and control complexity Proceedings of the Custom Integrated Circuits Conference. 571-574. DOI: 10.1109/CICC.2007.4405796  0.4
2008 Chaudhary V, Chen TH, Sheerin F, Clark LT. Critical race-free low-power NAND match line content addressable memory tagged cache memory Iet Computers and Digital Techniques. 2: 40-44. DOI: 10.1049/Iet-Cdt:20070040  0.478
2008 Haigh JR, Clark LT. High performance set associative translation lookaside buffers for low power microprocessors Integration, the Vlsi Journal. 41: 509-523. DOI: 10.1016/J.Vlsi.2007.11.003  0.395
2007 Li Z, Venugopal S, Shringarpure R, Allee DR, Clark LT. Noise-margin analysis of a-Si:H digital circuits Journal of the Society For Information Display. 15: 251-259. DOI: 10.1889/1.2723882  0.439
2007 Badrudduza SA, Samson G, Clark LT. LCSRAM: A leakage controlled six-transistor static random access memory cell with intrinsically high read stability Proceedings of the Ieee International Conference On Vlsi Design. 621-626. DOI: 10.1109/VLSID.2007.96  0.405
2007 Mohr KC, Clark LT, Holbert KE. A 130-nm RHBD SRAM with high speed SET and area efficient TIP mitigation Ieee Transactions On Nuclear Science. 54: 2092-2099. DOI: 10.1109/Tns.2007.910867  0.513
2007 Chen TH, Chen J, Clark LT, Knudsen JE, Samson G. Ultra-low power radiation hardened by design memory circuits Ieee Transactions On Nuclear Science. 54: 2004-2011. DOI: 10.1109/Tns.2007.909909  0.52
2007 Clark LT, Mohr KC, Holbert KE, Yao X, Knudsen J, Shah H. Optimizing radiation hard by design SRAM cells Ieee Transactions On Nuclear Science. 54: 2078-2086. DOI: 10.1109/Tns.2007.909482  0.4
2007 Hindman ND, Wang Z, Clark LT, Allee DR. Experimentally measured input referred voltage offsets and kickback noise in RHBD analog comparator arrays Ieee Transactions On Nuclear Science. 54: 2073-2079. DOI: 10.1109/Tns.2007.908654  0.595
2007 Mohr KC, Samson G, Clark LT. A radiation hardened by design register file with lightweight error detection and correction Ieee Transactions On Nuclear Science. 54: 1335-1342. DOI: 10.1109/Tns.2007.903173  0.432
2007 Shringarpure R, Venugopal S, Li Z, Clark LT, Allee DR, Bawolek E, Toy D. Circuit simulation of threshold-voltage degradation in a-Si:H TFTs fabricated at 175 °C Ieee Transactions On Electron Devices. 54: 1781-1783. DOI: 10.1109/Ted.2007.899667  0.396
2007 Cao Y, Clark LT. Mapping statistical process variations toward circuit performance variability: An analytical modeling approach Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 1866-1873. DOI: 10.1109/Tcad.2007.895613  0.404
2007 Clark LT, Mohr KC, Holbert KE. Reverse-body biasing for radiation-hard by design logic gates Annual Proceedings - Reliability Physics (Symposium). 582-583. DOI: 10.1109/RELPHY.2007.369961  0.391
2007 Mohr KC, Clark LT. Experimental characterization and application of circuit architecture level single event transient mitigation Annual Proceedings - Reliability Physics (Symposium). 312-317. DOI: 10.1109/RELPHY.2007.369909  0.415
2007 Badrudduza SA, Clark LT. Six and Seven Transistor Leakage Suppressed SRAM Cells with Improved Read Stability Proceedings of the Ieee 2007 Custom Integrated Circuits Conference, Cicc 2007. 225-228. DOI: 10.1109/CICC.2007.4405719  0.443
2006 Venugopal SM, Allee DR, Li Z, Clark LT. Threshold-voltage recovery of a-Si:H digital circuits Journal of the Society For Information Display. 14: 1053-1057. DOI: 10.1889/1.2393030  0.382
2006 Badrudduza SA, Samson G, Clark LT. Static Random Access Memory Cells with Intrinsically High Read Stability and Low Standby Power Journal of Low Power Electronics. 2: 412-424. DOI: 10.1166/Jolpe.2006.102  0.374
2006 Chen T, Chen J, Clark LT. Subthreshold to Above Threshold Level Shifter Design Journal of Low Power Electronics. 2: 251-258. DOI: 10.1166/Jolpe.2006.071  0.329
2006 Chaudhary V, Clark LT. Low-power high-performance NAND match line content addressable memories Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 14: 895-905. DOI: 10.1109/Tvlsi.2006.878476  0.446
2006 Knudsen JE, Clark LT. An area and power efficient radiation hardened by design flip-flop Ieee Transactions On Nuclear Science. 53: 3392-3399. DOI: 10.1109/Tns.2006.886199  0.464
2006 Chen J, Clark LT, Chen TH. An ultra-low-power memory with a subthreshold power supply voltage Ieee Journal of Solid-State Circuits. 41: 2344-2353. DOI: 10.1109/Jssc.2006.881549  0.471
2006 Samson G, Clark LT. A 0.13 μm low-power race-free programmable logic array Proceedings of the Custom Integrated Circuits Conference. 313-316. DOI: 10.1109/CICC.2006.320899  0.415
2006 Samson G, Clark LT. Circuit architecture for low-power race-free programmable logic arrays Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 2006: 416-421.  0.406
2006 Zi Li SV, Shringarpure R, Allee DR, Clark LT. Late-news poster: An analytical lifetime model for digital a-Si:H circuits Digest of Technical Papers - Sid International Symposium. 37: 270-273.  0.333
2005 McIver JK, Clark LT. Reducing radiation-hardened digital circuit power consumption Ieee Transactions On Nuclear Science. 52: 2503-2509. DOI: 10.1109/Tns.2005.861082  0.514
2005 Chen J, Clark LT, Cao Y. Maximum fan-in/out Ieee Circuits and Devices Magazine. 21: 12-20. DOI: 10.1109/Mcd.2005.1578583  0.493
2005 Haigh JR, Wilkerson MW, Miller JB, Beatty TS, Strazdus SJ, Clark LT. A low-power 2.5-GHz 90-nm level 1 cache and memory management unit Ieee Journal of Solid-State Circuits. 40: 1190-1199. DOI: 10.1109/Jssc.2005.845971  0.471
2005 Clark LT, Ricci F, Biyani M. Low standby power state storage for sub-130-nm technologies Ieee Journal of Solid-State Circuits. 40: 498-506. DOI: 10.1109/Jssc.2004.840987  0.473
2005 Chen J, Clark LT, Cao Y. Robust design of high fan-in/out subthreshold circuits Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 2005: 405-410. DOI: 10.1109/ICCD.2005.96  0.421
2005 Wissmiller KR, Knudsen JE, Alward TJ, Li ZP, Allee DR, Clark LT. Reducing power in flexible a-Si digital circuits while preserving state Proceedings of the Custom Integrated Circuits Conference. 2005: 216-219. DOI: 10.1109/CICC.2005.1568646  0.357
2004 Clark LT, Morrow M, Brown W. Reverse-body bias and supply collapse for low effective standby power Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 12: 947-956. DOI: 10.1109/Tvlsi.2004.832930  0.457
2004 Clark LT, Patel R, Beatty TS. Managing Standby and Active Mode Leakage Power in Deep Sub-micron Design Proceedings of the International Symposium On Low Power Electronics and Design. 2004: 274-279. DOI: 10.1109/LPE.2004.241060  0.348
2004 Maloney TJ, Poon SS, Clark LT. Methods for designing low-leakage ESD power supply clamps Journal of Electrostatics. 62: 85-97. DOI: 10.1016/J.Elstat.2004.03.005  0.472
2004 Clark LT, McCarroll DW, Bawolek EJ. Characterization and debug of reverse-body bias low-power modes Electronic Device Failure Analysis. 6: 13-21.  0.358
2003 Maloney TJ, Poon SS, Clark LT. Methods for designing low-leakage power supply clamps Electrical Overstress/Electrostatic Discharge Symposium Proceedings. 2003.  0.393
2001 Clark LT, Hoffman EJ, Miller J, Biyani M, Liao Y, Strazdus S, Morrow M, Velarde KE, Yarch MA. An embedded 32-b microprocessor core for low-power and high-performance applications Ieee Journal of Solid-State Circuits. 36: 1599-1608. DOI: 10.1109/4.962279  0.455
1996 Clark LT, Taylor GF. High fan-in circuit design Ieee Journal of Solid-State Circuits. 31: 91-96. DOI: 10.1109/4.485870  0.51
1994 Krick RF, Clark LT, Deleganes DJ, Wong KL, Fernando R, Debnath G, Banik J. A 150 MHz 0.6 μm BiCMOS Superscalar Microprocessor Ieee Journal of Solid-State Circuits. 29: 1455-1463. DOI: 10.1109/4.340418  0.438
1993 Clark LT, Gloerstad T, Grondint RO, Dey SK. Measurement and simulation of partial switching in ferroelectric pzt thin-films Integrated Ferroelectrics. 3: 309-320. DOI: 10.1080/10584589308216686  0.351
1992 Gloerstad TK, Grondin RO, Clark LT, Dey SK. A Pulse Generation Circuit for Improved Measurement of Current Transients in Ferroelectric Thin Films Ieee Transactions On Instrumentation and Measurement. 41: 716-719. DOI: 10.1109/19.177350  0.344
1991 Clark LT, Dey SK, Grondin RO. Ferroelectric thinfilm memory for electrically programmable ic neural networks Ferroelectrics. 116: 205-213. DOI: 10.1080/00150199108007943  0.315
1990 Rao A, Walker MR, Clark LT, Akers LA, Grondin RO. VLSI implementation of neural classifiers Neural Computation. 2: 35-43. DOI: 10.1162/Neco.1990.2.1.35  0.315
1989 Clark LT, Grondin RO. A Pipelined Associative Memory Implemented in VLSI Ieee Journal of Solid-State Circuits. 24: 28-34. DOI: 10.1109/4.16298  0.43
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