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Hanho Lee, Ph.D. - Publications

Affiliations: 
2000 University of Minnesota, Twin Cities, Minneapolis, MN 
Area:
Electronics and Electrical Engineering
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52 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2023 Lee J, Duong PN, Lee H. Configurable Encryption and Decryption Architectures for CKKS-Based Homomorphic Encryption. Sensors (Basel, Switzerland). 23. PMID 37687844 DOI: 10.3390/s23177389  0.306
2020 Tan TN, Nguyen TTB, Lee H. High Efficiency Ring-LWE Cryptoprocessor Using Shared Arithmetic Components Electronics. 9: 1075. DOI: 10.3390/Electronics9071075  0.404
2020 Pham TX, Tan TN, Lee H. Minimal-Set Trellis Min-Max Decoder Architecture for Nonbinary LDPC Codes Ieee Transactions On Circuits and Systems Ii-Express Briefs. 1-1. DOI: 10.1109/Tcsii.2020.3011220  0.34
2020 Duong-Ngoc P, Tan TN, Lee H. Efficient NewHope Cryptography Based Facial Security System on a GPU Ieee Access. 8: 108158-108168. DOI: 10.1109/Access.2020.3000316  0.314
2019 Nguyen TTB, Tan TN, Lee H. Efficient QC-LDPC Encoder for 5G New Radio Electronics. 8: 668. DOI: 10.3390/Electronics8060668  0.4
2019 Tan TN, Lee H. Efficient-Scheduling Parallel Multiplier-Based Ring-LWE Cryptoprocessors Electronics. 8: 413. DOI: 10.3390/Electronics8040413  0.425
2019 Tan TN, Lee H. High-Secure Fingerprint Authentication System Using Ring-LWE Cryptography Ieee Access. 7: 23379-23387. DOI: 10.1109/Access.2019.2899359  0.322
2019 Thi HP, Lee H, Pham XN. Half-row modified two-extra-column trellis min-max decoder architecture for nonbinary LDPC codes Integration. 69: 234-241. DOI: 10.1016/J.Vlsi.2019.04.005  0.464
2019 Nguyen TTB, Lee H. Low-complexity multi-mode multi-way split-row layered LDPC decoder for gigabit wireless communications Integration. 65: 189-200. DOI: 10.1016/J.Vlsi.2018.12.004  0.451
2018 Kim T, Lee H. High-performance Syndrome-based SD-BCH Decoder Architecture using Hard-decision Kernel Journal of Semiconductor Technology and Science. 18: 694-703. DOI: 10.5573/Jsts.2018.18.6.694  0.323
2018 Oh S, Lee H. High-performance Parallel Concatenated Polar-CRC Decoder Architecture Journal of Semiconductor Technology and Science. 18: 560-567. DOI: 10.5573/Jsts.2018.18.5.560  0.361
2018 Thi HP, Lee H. Basic-Set Trellis Min–Max Decoder Architecture for Nonbinary LDPC Codes With High-Order Galois Fields Ieee Transactions On Very Large Scale Integration Systems. 26: 496-507. DOI: 10.1109/Tvlsi.2017.2775646  0.447
2017 Ajaz S, Nguyen TTB, Lee H. An Area-efficient Half-row Pipelined Layered LDPC Decoder Architecture Journal of Semiconductor Technology and Science. 17: 845-853. DOI: 10.5573/Jsts.2017.17.6.845  0.343
2017 Nguyen TTB, Lee H. High-throughput Low-complexity Mixed-radix FFT Processor using a Dual-path Shared Complex Constant Multiplier Journal of Semiconductor Technology and Science. 17: 101-109. DOI: 10.5573/Jsts.2017.17.1.101  0.474
2017 Thi HP, Lee H. Two-Extra-Column Trellis Min–Max Decoder Architecture for Nonbinary LDPC Codes Ieee Transactions On Very Large Scale Integration Systems. 25: 1787-1791. DOI: 10.1109/Tvlsi.2017.2647985  0.45
2017 Thi HP, Ajaz S, Lee H. High-throughput partial-parallel block-layered decoding architecture for nonbinary LDPC codes Integration. 59: 52-63. DOI: 10.1016/J.Vlsi.2017.05.005  0.477
2016 Jung B, Kim T, Lee H. Low-complexity non-iterative soft-decision BCH decoder architecture for WBAN applications Journal of Semiconductor Technology and Science. 16: 488-496. DOI: 10.5573/Jsts.2016.16.4.488  0.428
2016 Nguyen TT, Lee H. Efficient Algorithm and Architecture for Elliptic Curve Cryptographic Processor Journal of Semiconductor Technology and Science. 16: 118-125. DOI: 10.5573/Jsts.2016.16.1.118  0.437
2016 Yun HR, Lee H. Simplified merged processing element for successive-cancellation polar decoder Electronics Letters. 52: 270-272. DOI: 10.1049/El.2015.3432  0.419
2015 Kim C, Yun H, Ajaz S, Lee H. High-Throughput Low-Complexity Successive-Cancellation Polar Decoder Architecture using One's Complement Scheme Journal of Semiconductor Technology and Science. 15: 427-435. DOI: 10.5573/Jsts.2015.15.3.427  0.437
2015 Ajaz S, Lee H. Efficient multi-Gb/s multi-mode LDPC decoder architecture for IEEE 802.11ad applications Integration. 51: 21-36. DOI: 10.1016/J.Vlsi.2015.05.001  0.405
2014 Ajaz S, Lee H. Pipeline-Aware QC-IRA-LDPC Code and Efficient Decoder Architecture Journal of the Institute of Electronics Engineers of Korea. 51: 72-79. DOI: 10.5573/Ieie.2014.51.10.072  0.368
2013 Yeon J, Yang S, Kim C, Lee H. Low-Complexity Triple-Error-Correcting Parallel BCH Decoder Journal of Semiconductor Technology and Science. 13: 465-472. DOI: 10.5573/Jsts.2013.13.5.465  0.418
2013 Lee H, Ajaz S. High-Throughput QC-LDPC Decoder Architecture for Multi-Gigabit WPAN Systems Journal of the Institute of Electronics Engineers of Korea. 50: 104-113. DOI: 10.5573/Ieek.2013.50.2.104  0.464
2013 Hwang S, Lee H. Block-Circulant RS-LDPC Code: Code Construction and Efficient Decoder Design Ieee Transactions On Very Large Scale Integration Systems. 21: 1337-1341. DOI: 10.1109/Tvlsi.2012.2210452  0.397
2013 Cho T, Lee H. A high-speed low-complexity modified Radix-25 FFT processor for high rate WPAN applications Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 21: 187-191. DOI: 10.1109/Tvlsi.2011.2182068  0.46
2013 Ajaz S, Lee H. Reduced-complexity local switch based multi-mode QC-LDPC decoder architecture for Gbit wireless communication Electronics Letters. 49: 1246-1248. DOI: 10.1049/El.2013.1673  0.425
2012 Park JI, Lee H. A high-speed low-complexity time-multiplexing reed-solomon-based FEC architecture for optical communications Ieice Transactions On Fundamentals of Electronics, Communications and Computer Sciences. 2424-2429. DOI: 10.1587/Transfun.E95.A.2424  0.474
2011 Kim Y, Choi C, Lee H. Low Complexity Filter Architecture for ATSC Terrestrial Broadcasting DTV Systems Ieice Transactions On Fundamentals of Electronics, Communications and Computer Sciences. 94: 937-945. DOI: 10.1587/Transfun.E94.A.937  0.41
2011 Jung K, Lee H. Low-Complexity Multi-Mode Memory-Based FFT Processor for DVB-T2 Applications Ieice Transactions On Fundamentals of Electronics, Communications and Computer Sciences. 94: 2376-2383. DOI: 10.1587/Transfun.E94.A.2376  0.377
2011 Choi C, Ahn H, Lee H. High-Throughput Low-Complexity Four-Parallel Reed-Solomon Decoder Architecture for High-Rate WPAN Systems Ieice Transactions On Communications. 94: 1332-1338. DOI: 10.1587/Transcom.E94.B.1332  0.449
2011 Kim S, Sobelman GE, Lee H. A Reduced-Complexity Architecture for LDPC Layered Decoding Schemes Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 19: 1099-1103. DOI: 10.1109/Tvlsi.2010.2043965  0.682
2011 Park JI, Lee H. Area-efficient truncated Berlekamp-Massey architecture for Reed-Solomon decoder Electronics Letters. 47: 241-243. DOI: 10.1049/El.2010.3369  0.438
2010 Park J, Lee K, Choi C, Lee H. High-Speed Low-Complexity Reed-Solomon Decoder using Pipelined Berlekamp-Massey Algorithm and Its Folded Architecture Journal of Semiconductor Technology and Science. 10: 193-202. DOI: 10.5573/Jsts.2010.10.3.193  0.446
2010 Yoon S, Lee H, Lee K. High-Speed Two-Parallel Concatenated BCH-Based Super-FEC Architecture for Optical Communications Ieice Transactions On Fundamentals of Electronics, Communications and Computer Sciences. 93: 769-777. DOI: 10.1587/Transfun.E93.A.769  0.463
2008 Lee S, Choi C, Lee H. Two-parallel Reed-Solomon based FEC architecture for optical communications Ieice Electronics Express. 5: 374-380. DOI: 10.1587/Elex.5.374  0.386
2008 Lee J, Lee H. A High-Speed Two-Parallel Radix-24 FFT/IFFT Processor for MB-OFDM UWB Systems Ieice Transactions On Fundamentals of Electronics, Communications and Computer Sciences. 91: 1206-1211. DOI: 10.1093/Ietfec/E91-A.4.1206  0.483
2008 Lee S, Lee H. A High-Speed Pipelined Degree-Computationless Modified Euclidean Algorithm Architecture for Reed-Solomon Decoders Ieice Transactions On Fundamentals of Electronics, Communications and Computer Sciences. 91: 830-835. DOI: 10.1093/Ietfec/E91-A.3.830  0.448
2007 Choi C, Lee H. A Self-Reconfigurable Adaptive FIR Filter System on Partial Reconfiguration Platform Ieice Transactions On Information and Systems. 90: 1932-1938. DOI: 10.1093/Ietisy/E90-D.12.1932  0.326
2007 Shin CH, Choi S, Lee H, Pack JK. A design and performance of 4-parallel MB-OFDM UWB receiver Ieice Transactions On Communications. 672-675. DOI: 10.1093/Ietcom/E90-B.3.672  0.355
2005 Lee H. A high-speed low-complexity Reed-Solomon decoder for optical communications Ieee Transactions On Circuits and Systems Ii-Express Briefs. 52: 461-465. DOI: 10.1109/Tcsii.2005.850452  0.439
2004 LEE H, SOBELMAN GE. VLSI DESIGN OF DIGIT-SERIAL FPGA ARCHITECTURE Journal of Circuits, Systems and Computers. 13: 17-52. DOI: 10.1142/S021812660400126X  0.686
2004 Lee H. A power-aware scalable pipelined booth multiplier Proceedings - Ieee International Soc Conference. 123-126. DOI: 10.1093/Ietfec/E88-A.11.3230  0.379
2003 Lee H. High-speed VLSI architecture for parallel reed-solomon decoder Proceedings - Ieee International Symposium On Circuits and Systems. 2. DOI: 10.1109/Tvlsi.2003.810782  0.432
2003 Lee H. High-speed VLSI architecture for parallel Reed-Solomon decoder Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 11: 288-294. DOI: 10.1109/TVLSI.2003.810782  0.329
2003 Lee H, Azam A. Pipelined recursive modified Euclidean algorithm block for low-complexity, high-speed Reed-Solomon decoder Electronics Letters. 39: 1371-1372. DOI: 10.1049/El:20030886  0.409
2003 Lee H, Sobelman GE. Performance evaluation and optimal design for FPGA-based digit-serial DSP functions Computers & Electrical Engineering. 29: 357-377. DOI: 10.1016/S0045-7906(01)00043-X  0.69
2002 Lee H, Sobelman GE. FPGA-based digit-serial CSD FIR filter for image signal format conversion Microelectronics Journal. 33: 501-508. DOI: 10.1016/S0026-2692(01)00137-9  0.66
2001 Lee H. Modified euclidean algorithm block for high-speed Reed-Solomon decoder Electronics Letters. 37: 903-904. DOI: 10.1049/El:20010628  0.383
2001 Lee H. A VLSI design of a high-speed Reed-Solomon decoder Proceedings of the Annual Ieee International Asic Conference and Exhibit. 316-320.  0.319
1998 Lee H, Sobelman GE. A comparative study of glitch-free true single-phase clocked D flip-flop circuits at low supply voltage Microelectronics Journal. 29: 1025-1031. DOI: 10.1016/S0026-2692(98)00075-5  0.64
1998 Lee H, Sobelman GE. New XOR/XNOR and full adder circuits for low voltage, low power applications Microelectronics Journal. 29: 509-517. DOI: 10.1016/S0026-2692(97)00120-1  0.357
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