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Mansun J. Chan - Publications

Affiliations: 
Electronic and Computer Engineering Hong Kong University of Science and Technology, Clear Water Bay, Kowloon, Hong Kong 
Area:
Electronics and Electrical Engineering
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Year Citation  Score
2023 Zhang L, Chan M. Editorial: Hardware implementation of spike-based neuromorphic computing and its design methodologies. Frontiers in Neuroscience. 16: 1113983. PMID 36685232 DOI: 10.3389/fnins.2022.1113983  0.358
2020 Estrada CJ, Xiao Y, Xu C, Chan M. Physical Model of Current-Assisted Photonic Demodulator (CAPD) for Time-of-Flight CMOS Image Sensor Ieee Transactions On Electron Devices. 67: 2825-2830. DOI: 10.1109/Ted.2020.2995349  0.349
2020 Hu H, Liu D, Chen X, Dong D, Cui X, Liu M, Lin X, Zhang L, Chan M. A Compact Phase Change Memory Model With Dynamic State Variables Ieee Transactions On Electron Devices. 67: 133-139. DOI: 10.1109/Ted.2019.2956193  0.603
2020 Ahmed Z, Shi Q, Ma Z, Zhang L, Guo H, Chan M. Analytical Monolayer MoS 2 MOSFET Modeling Verified by First Principle Simulations Ieee Electron Device Letters. 41: 171-174. DOI: 10.1109/Led.2019.2952382  0.59
2020 Chen X, Hu H, Huang X, Cai W, Liu M, Lam C, Lin X, Zhang L, Chan M. A SPICE Model of Phase Change Memory for Neuromorphic Circuits Ieee Access. 8: 95278-95287. DOI: 10.1109/Access.2020.2995907  0.632
2020 Cheng W, He M, Lei S, Wang L, Wu J, Zeng F, Hu Q, Wang Q, Zhao F, Chan M, Xia G(, Yu H. Increasing threshold voltage and reducing leakage of AlGaN/GaN HEMTs using dual-layer SiN x stressors Semiconductor Science and Technology. 35: 45010. DOI: 10.1088/1361-6641/Ab73Ea  0.33
2019 Xiao Y, Ahmed Z, Ma Z, Zhou C, Zhang L, Chan M. Low Temperature Synthesis of High-Density Carbon Nanotubes on Insulating Substrate. Nanomaterials (Basel, Switzerland). 9. PMID 30901961 DOI: 10.3390/Nano9030473  0.454
2019 Zhang L, Ma C, Xiao Y, Zhang H, Lin X, Chan M. A Dynamic Time Evolution Method for Concurrent Device-Circuit Aging Simulations Ieee Transactions On Electron Devices. 66: 184-190. DOI: 10.1109/Ted.2018.2882832  0.625
2019 Zhang L, Wang L, Wu W, Chan M. Modeling Current–Voltage Characteristics of Bilayer Organic Light-Emitting Diodes Ieee Transactions On Electron Devices. 66: 139-145. DOI: 10.1109/Ted.2018.2843681  0.523
2019 Zhou S, Li K, Chen Y, Liao S, Zhang H, Chan M. Phase Change Memory Cell With Reconfigured Electrode for Lower RESET Voltage Ieee Journal of the Electron Devices Society. 7: 1072-1079. DOI: 10.1109/Jeds.2019.2948254  0.347
2019 Ma Z, Prawoto C, Ahmed Z, Xiao Y, Zhang L, Zhou C, Chan M. Control of hexagonal boron nitride dielectric thickness by single layer etching Journal of Materials Chemistry C. 7: 6273-6278. DOI: 10.1039/C9Tc00896A  0.472
2019 Kabir HD, Chan M. Polycrystalline transistor with multiple thresholds Microelectronics Journal. 83: 126-130. DOI: 10.1016/J.Mejo.2018.12.002  0.399
2018 Zhang X, Zhang L, Ahmed Z, Chan M. Origin of Nonideal Graphene-Silicon Schottky Junction Ieee Transactions On Electron Devices. 65: 1995-2002. DOI: 10.1109/Ted.2018.2812200  0.505
2018 Wu W, Chen J, Wang J, Zhou L, Tao H, Zou J, Xu M, Wang L, Peng J, Chan M. High-Resolution Flexible AMOLED Display Integrating Gate Driver by Metal–Oxide TFTs Ieee Electron Device Letters. 39: 1660-1663. DOI: 10.1109/Led.2018.2871045  0.403
2018 Zhang L, Song D, Xiao Y, Lin X, Chan M. On the Formulation of Self-Heating Models for Circuit Simulation Ieee Journal of the Electron Devices Society. 6: 291-297. DOI: 10.1109/Jeds.2018.2801301  0.585
2018 Kabir HMD, Ahmed Z, Kariyadan R, Zhang L, Chan M. Circular Electrodes to Reduce the Current Variation of OTFTS With the Drop-casted Semiconducting Layer Solid-State Electronics. 144: 49-53. DOI: 10.1016/J.Sse.2018.02.017  0.53
2017 Lin H, Chan WC, Lee WK, Chen Z, Chan M, Zhang M. High-Current Drivability Fibonacci Charge Pump With Connect–Point–Shift Enhancement Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 25: 2164-2173. DOI: 10.1109/Tvlsi.2017.2676822  0.342
2017 Wu J, Zhan F, Zhou L, Wu W, Xu M, Wang L, Yao R, Peng J, Chan M. A Low-Power Ring Oscillator Using Pull-Up Control Scheme Integrated by Metal–Oxide TFTs Ieee Transactions On Electron Devices. 64: 4946-4951. DOI: 10.1109/Ted.2017.2759226  0.319
2017 Kabir HMD, Ahmed Z, Zhang L, Chan M. Coil-Shaped Electrodes to Reduce the Current Variation of Drop-Casted OTFTs Ieee Electron Device Letters. 38: 645-648. DOI: 10.1109/Led.2017.2679201  0.528
2017 Sarfraz K, He J, Chan M. A 140-mV Variation-Tolerant Deep Sub-Threshold SRAM in 65-nm CMOS Ieee Journal of Solid-State Circuits. 52: 2215-2220. DOI: 10.1109/Jssc.2017.2707392  0.353
2017 Wang P, Chen Y, Li S, Raju S, Wang L, Zhang L, Lin X, Song Z, Chan M. Low Power Phase Change Memory With Vertical Carbon Nanotube Electrode Ieee Journal of the Electron Devices Society. 5: 362-366. DOI: 10.1109/Jeds.2017.2734858  0.588
2017 Zhang L, Chan M. Artificial neural network design for compact modeling of generic transistors Journal of Computational Electronics. 16: 825-832. DOI: 10.1007/S10825-017-0984-9  0.543
2016 He J, Zhang X, Chan M, Wu W, Zhao W, Wang W, He P, Song L. A Physics Based Analytic Model for Gate All Around MOSFETs with SiO 2 -Core Si-Shell Architecture Journal of Computational and Theoretical Nanoscience. 13: 4866-4871. DOI: 10.1166/Jctn.2016.5358  0.339
2016 Xiao Y, Lin X, Lou H, Zhang B, Zhang L, Chan M. A Short Channel Double-Gate Junctionless Transistor Model Including the Dynamic Channel Boundary Effect Ieee Transactions On Electron Devices. 63: 4661-4667. DOI: 10.1109/Ted.2016.2620240  0.637
2016 Dong Y, Zhang L, Li X, Lin X, Chan M. A Compact Model for Double-Gate Heterojunction Tunnel FETs Ieee Transactions On Electron Devices. 63: 4506-4513. DOI: 10.1109/Ted.2016.2604001  0.665
2016 Ahmed Z, Zhang L, Sarfraz K, Chan M. Modeling CNTFET Performance Variation Due to Spatial Distribution of Carbon Nanotubes Ieee Transactions On Electron Devices. 63: 3776-3781. DOI: 10.1109/Ted.2016.2586961  0.485
2016 Lin X, Zhang B, Xiao Y, Lou H, Zhang L, Chan M. Analytical Current Model for Long-Channel Junctionless Double-Gate MOSFETs Ieee Transactions On Electron Devices. DOI: 10.1109/Ted.2016.2520558  0.599
2016 Zhou S, Liu J, Deng Q, Xie C, Chan M. Effect of Near-Field Diffraction in Photolithography of Hexagonal Arrays for Dichroic Filters Ieee Photonics Journal. 8. DOI: 10.1109/Jphot.2016.2594032  0.302
2016 Lin H, Chan WC, Lee WK, Chen Z, Chan M, Zhang M. A High Conversion Ratio Component-Efficient Charge Pump for Display Drivers Journal of Display Technology. 12: 1057-1063. DOI: 10.1109/Jdt.2016.2578640  0.355
2016 Zhou C, Zhao Y, Raju S, Wang Y, Lin Z, Chan M, Chai Y. Carrier Type Control of WSe2 Field-Effect Transistors by Thickness Modulation and MoO3 Layer Doping Advanced Functional Materials. DOI: 10.1002/Adfm.201600292  0.341
2015 Guo J, Ng W, Yuan J, Li S, Chan M. A 200-Channel Area-Power-Efficient Chemical and Electrical Dual-Mode Acquisition IC for the Study of Neurodegenerative Diseases. Ieee Transactions On Biomedical Circuits and Systems. PMID 26529782 DOI: 10.1109/Tbcas.2015.2468052  0.352
2015 Hu Y, Wang H, Du C, Ma M, Chan M, He J, Wang G. A High-Voltage (>600 V) N-Island LDMOS With Step-Doped Drift Region in Partial SOI Technology Ieee Transactions On Electron Devices. DOI: 10.1109/Ted.2015.2487345  0.379
2015 Ahmed Z, Zhang L, Chan M. Gate Capacitance Model for Aligned Carbon Nanotube FETs With Arbitrary CNT Spacing Ieee Transactions On Electron Devices. DOI: 10.1109/Ted.2015.2484384  0.535
2015 Salahuddin SM, Chan M. Eight-FinFET fully differential SRAM cell with enhanced read and write voltage margins Ieee Transactions On Electron Devices. 62: 2014-2021. DOI: 10.1109/Ted.2015.2424376  0.329
2015 Li D, Zhang B, Lou H, Zhang L, Lin X, Chan M. Comparative Analysis of Carrier Statistics on MOSFET and Tunneling FET Characteristics Ieee Journal of the Electron Devices Society. 3: 447-451. DOI: 10.1109/Jeds.2015.2475163  0.652
2015 Kabir HMD, Chan M. SRAM precharge system for reducing write power Hkie Transactions Hong Kong Institution of Engineers. 22: 1-8. DOI: 10.1080/1023697X.2014.970761  0.326
2014 Raju S, Wu R, Chan M, Yue CP. Modeling of Mutual Coupling Between Planar Inductors in Wireless Power Applications Ieee Transactions On Power Electronics. 29: 481-490. DOI: 10.1109/Tpel.2013.2253334  0.38
2014 Zhang A, Zhang L, Tang Z, Cheng X, Wang Y, Chen KJ, Chan M. Analytical Modeling of Capacitances for GaN HEMTs, Including Parasitic Components Ieee Transactions On Electron Devices. 61: 755-761. DOI: 10.1109/Ted.2014.2298255  0.576
2014 Huang JZ, Zhang L, Chew WC, Yam CY, Jiang LJ, Chen GH, Chan M. Model order reduction for quantum transport simulation of band-to-band tunneling devices Ieee Transactions On Electron Devices. 61: 561-568. DOI: 10.1109/Ted.2013.2295983  0.542
2014 Zhang L, Chan M. SPICE Modeling of Double-Gate Tunnel-FETs Including Channel Transports Ieee Transactions On Electron Devices. 61: 300-307. DOI: 10.1109/Ted.2013.2295237  0.556
2014 Wang L, Sun L, Han D, Wang Y, Chan M, Zhang S. A Hybrid a-Si and Poly-Si TFTs Technology for AMOLED Pixel Circuits Ieee\/Osa Journal of Display Technology. 10: 317-320. DOI: 10.1109/Jdt.2014.2301554  0.329
2013 Lou H, Li D, Dong Y, Lin X, Yang S, He J, Chan M. Effects of Fin Sidewall Angle on Subthreshold Characteristics of Junctionless Multigate Transistors Japanese Journal of Applied Physics. 52: 104302. DOI: 10.7567/Jjap.52.104302  0.513
2013 He J, Leung WY, Man TY, He L, Liang H, Zhang A, He Q, Du C, He X, Chan M. Design and Verification of a High Performance LED Driver with an Efficient Current Sensing Architecture Circuits and Systems. 4: 393-400. DOI: 10.4236/Cs.2013.45052  0.354
2013 He J, Zhou Z, Yu C, He L, Ye Y, Chan M. Non-charge-sheet analytic model for ideal retrograde doping MOSFETs Journal of Computational and Theoretical Nanoscience. 10: 232-239. DOI: 10.1166/Jctn.2013.2684  0.327
2013 Zhang L, He J, Chen Q, Ma Y, Wang R, Ma Y, Zhao W, Chan M, Chen A. A Nonlinear Poisson-Schrodinger Solver Under Cylindrical Coordinate for Quantum Effect in Nanowire MOSFET Journal of Computational and Theoretical Nanoscience. 10: 73-77. DOI: 10.1166/Jctn.2013.2660  0.447
2013 Zhang L, Zahid F, Zhu Y, Liu L, Wang J, Guo H, Chan PCH, Chan M. First Principles simulations of nanoscale silicon devices with uniaxial strain Ieee Transactions On Electron Devices. 60: 3527-3533. DOI: 10.1109/Ted.2013.2275231  0.532
2013 Zhou C, Yang Y, Cai H, Ren T, Chan M, Yang CY. Temperature-Compensated High-Frequency Surface Acoustic Wave Device Ieee Electron Device Letters. 34: 1572-1574. DOI: 10.1109/Led.2013.2283305  0.303
2013 Lou H, Li D, Dong Y, Lin X, He J, Yang S, Chan M. Suppression of tunneling leakage current in junctionless nanowire transistors Semiconductor Science and Technology. 28: 125016. DOI: 10.1088/0268-1242/28/12/125016  0.56
2013 Zhang L, Mei J, Zhang X, Tao J, Hu Y, He J, Chan M. A Comparative Study of Ballistic Transport Models for Nanowire MOSFETs Chinese Physics Letters. 30: 117102-117102. DOI: 10.1088/0256-307X/30/11/117102  0.521
2012 Zhang L, Wang S, Ma C, He J, Xu C, Ma Y, Ye Y, Liang H, Chen Q, Chan M. Gate underlap design for short channel effects control in cylindrical gate-all-around MOSFETs based on an analytical model Iete Technical Review. 29: 29-35. DOI: 10.4103/0256-4602.93125  0.583
2012 Shi M, Song Y, Zhang Z, Sun L, Wang Q, He J, Chan M. An Explicit Surface Potential Model of Bulk-MOSFETs with Inclusion of Poly-Gate Accumulation, Depletion and Inversion Effects Journal of Computational and Theoretical Nanoscience. 9: 963-968. DOI: 10.1166/Jctn.2012.2125  0.355
2012 Chen Y, He J, Liang HL, Ma Y, Chen Q, Su Y, He HY, Chan M, Cao J. Model-Based Prediction of the Plasma Oscillation Excitation Response Characteristics of a High-Electron Mobility Transistor-Based Terahertz Photomixer with the Cap Region Journal of Computational and Theoretical Nanoscience. 9: 549-554. DOI: 10.1166/Jctn.2012.2059  0.32
2012 Zhang L, Lin X, He J, Chan M. An Analytical Charge Model for Double-Gate Tunnel FETs Ieee Transactions On Electron Devices. 59: 3217-3223. DOI: 10.1109/Ted.2012.2217145  0.655
2012 He H, Zheng X, He J, Chan M. Polynomial-Effective-Channel-Mobility-Based Above-Threshold Current Model for Undoped Polycrystalline-Silicon Thin-Film Transistors Consistent With Pao–Sah Model Ieee Transactions On Electron Devices. 59: 3130-3132. DOI: 10.1109/Ted.2012.2212905  0.429
2012 Li S, Cai Y, Han D, Wang Y, Sun L, Chan M, Zhang S. Low-Temperature ZnO TFTs Fabricated by Reactive Sputtering of Metallic Zinc Target Ieee Transactions On Electron Devices. 59: 2555-2558. DOI: 10.1109/Ted.2012.2205151  0.35
2012 He J, Chan WT, Wang C, Lou H, Wang R, Li L, Liang H, Wu W, Ye Y, Ma Y, Chen Q, He X, Chan M. A Compact CMOS Compatible Oxide Antifuse With Polysilicon Diode Driver Ieee Transactions On Electron Devices. 59: 2539-2541. DOI: 10.1109/Ted.2012.2201941  0.337
2012 Zhou X, Liu F, Zhang L, Wang C, He J, Zhang X, Chan M. Unified Scale Length for Four-Terminal Double-Gate MOSFETs Ieee Transactions On Electron Devices. 59: 1997-1999. DOI: 10.1109/Ted.2012.2196520  0.576
2012 Lou H, Zhang L, Zhu Y, Lin X, Yang S, He J, Chan M. A Junctionless Nanowire Transistor With a Dual-Material Gate Ieee Transactions On Electron Devices. 59: 1829-1836. DOI: 10.1109/Ted.2012.2192499  0.639
2012 Li L, Chui CO, He J, Chan M. One-time-programmable memory in LTPS TFT technology with metal-induced lateral crystallization Ieee Transactions On Electron Devices. 59: 145-150. DOI: 10.1109/Ted.2011.2171039  0.306
2012 Li L, Zhang L, Lin X, He J, Chui CO, Chan M. Phase-change memory with multifin thin-film-transistor driver technology Ieee Electron Device Letters. 33: 405-407. DOI: 10.1109/Led.2011.2181480  0.611
2012 Guo J, Yuan J, Huang J, Law JKY, Yeung CK, Chan M. 32.9 nV/rt Hz -60.6 dB THD dual-band micro-electrode array signal acquisition IC Ieee Journal of Solid-State Circuits. 47: 1209-1220. DOI: 10.1109/Jssc.2012.2185590  0.335
2012 Zhang J, He J, Zhou X, Zhang L, Ma Y, Chen Q, Zhang X, Yang Z, Wang R, Han Y, Chan M. A unified charge-based model for SOI MOSFETs applicable from intrinsic to heavily doped channel Chinese Physics B. 21: 47303. DOI: 10.1088/1674-1056/21/4/047303  0.579
2011 Zhang L, Zhou X, Xu Y, Chen L, Zhou W, Wang W, He J, Chan M. A unified drain current model for nanoscale double-gate and surrounding-gate MOSFETs incorporating velocity saturation. Journal of Nanoscience and Nanotechnology. 11: 10480-4. PMID 22408930 DOI: 10.1166/Jnn.2011.3983  0.606
2011 Zhang X, He J, Zhang L, Zhang J, Ma Y, Wu W, Wang W, Wang R, Gu X, Chan M. A rigorous and concise surface potential-based core model for the undoped symmetric double-gate metal-oxide-semiconductor field effect transistors Journal of Computational and Theoretical Nanoscience. 8: 1857-1862. DOI: 10.1166/Jctn.2011.1893  0.531
2011 Shi M, He J, Liu Z, Wang W, Zhao W, Wang R, Wu W, Ma Y, Zhang D, Bian W, Chan M, Zhang X, Zhang L. 3-D Numerical Simulation Study on 20 nm NMOSFET Design Journal of Computational and Theoretical Nanoscience. 8: 1498-1501. DOI: 10.1166/Jctn.2011.1841  0.467
2011 He J, Shi M, Zhang L, Zhang J, Liu C, Zhuang H, Chan M. Computation Efficient yet Accurate Surface Potential Based Analytic Model for Symmetric DG MOSFETs to Predict Current-Voltage Characteristics Journal of Computational and Theoretical Nanoscience. 8: 1548-1551. DOI: 10.1166/Jctn.2011.1827  0.584
2011 Zhang L, Lou H, He J, Chan M. Uniaxial Strain Effects on Electron Ballistic Transport in Gate-All-Around Silicon Nanowire MOSFETs Ieee Transactions On Electron Devices. 58: 3829-3836. DOI: 10.1109/Ted.2011.2165215  0.476
2011 Kwong KC, He J, Mok PKT, Chan M. Phase-change memory RESET model based on detailed cell cooling profile Ieee Transactions On Electron Devices. 58: 3635-3638. DOI: 10.1109/Ted.2011.2162843  0.701
2011 Li L, Lu K, Rajendran B, Happ TD, Lung H, Lam C, Chan M. Driving Device Comparison for Phase-Change Memory Ieee Transactions On Electron Devices. 58: 664-671. DOI: 10.1109/Ted.2010.2100082  0.379
2011 Zhang L, Li L, He J, Chan M. Modeling Short-Channel Effect of Elliptical Gate-All-Around MOSFET by Effective Radius Ieee Electron Device Letters. 32: 1188-1190. DOI: 10.1109/Led.2011.2159358  0.57
2011 Shi M, He J, Zhang L, Ma C, Zhou X, Lou H, Zhuang H, Wang R, Li Y, Ma Y, Wu W, Wang W, Chan M. Zero-Mask Contact Fuse for One-Time-Programmable Memory in Standard CMOS Processes Ieee Electron Device Letters. 32: 955-957. DOI: 10.1109/Led.2011.2147754  0.534
2011 Guo J, Yuan J, Huang J, Law J, Yeung CK, Chan M. Highly accurate dual-band cellular field potential acquisition for brain-machine interface Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 1: 461-468. DOI: 10.1109/Jetcas.2011.2174471  0.316
2010 Leung WY, Man TY, Zhang D, He J, Chan M. A high power switch-mode LED driver with an efficient current sensing scheme Journal of Low Power Electronics. 6: 133-140. DOI: 10.1166/Jolpe.2010.1063  0.337
2010 Zhang J, Zhang L, He J, Chan M. A noncharge-sheet channel potential and drain current model for dynamic-depletion silicon-on-insulator metal-oxide-semiconductor field-effect transistors Journal of Applied Physics. 107: 54507. DOI: 10.1063/1.3319656  0.596
2010 Zhang L, Ma C, He J, Lin X, Chan M. Analytical solution of subthreshold channel potential of gate underlap cylindrical gate-all-around MOSFET Solid-State Electronics. 54: 806-808. DOI: 10.1016/J.Sse.2010.03.020  0.572
2010 Wang Y, Yan Z, Zhu J, Zhang L, Lin X, He J, Cao J, Chan M. A generic numerical model for detection of terahertz radiation in MOS field-effect transistors Solid-State Electronics. 54: 791-795. DOI: 10.1016/J.Sse.2010.03.009  0.543
2010 Samanta P, Zhu C, Chan M. Comparison of electrical stress-induced charge carrier generation/trapping and related degradation of SiO2 and HfO2/SiO2 gate dielectric stacks Microelectronics Reliability. 50: 1907-1914. DOI: 10.1016/J.Microrel.2010.07.005  0.376
2010 Zhang L, Zhang J, Song Y, Lin X, He J, Chan M. Charge-based model for symmetric double-gate MOSFETs with inclusion of channel doping effect Microelectronics Reliability. 50: 1062-1070. DOI: 10.1016/J.Microrel.2010.04.005  0.659
2010 He J, Xing Z, Wang Y, Xi X, Chan M, Hu C. Retraction notice: Retraction notice to “Normalized mutual integral difference operator: A novel experimental method for extracting threshold voltage of MOSFETs” [Microelectron. J. 33 (2002) 667-670] Microelectronics Journal. 41: 693. DOI: 10.1016/J.Mejo.2010.09.001  0.303
2010 Zhang L, Ma C, He J, Lin X, Chan M. Analytical solution of subthreshold channel potential of gate underlap cylindrical gate-all-around MOSFET Journal of End-to-End-Testing. DOI: 10.1016/J.Endend.2010.06.030  0.536
2009 Chen Y, He J, Wang Y, Lin X, Zhang L, Chan M. Terahertz Wave Generation and Detection Analysis of Silicon Nanowire MOS Field-Effect Transistor Iete Technical Review. 26: 430-439. DOI: 10.4103/0256-4602.57828  0.494
2009 Ng RMY, Wang T, Liu F, Zuo X, He J, Chan M. Vertically Stacked Silicon Nanowire Transistors Fabricated by Inductive Plasma Etching and Stress-Limited Oxidation Ieee Electron Device Letters. 30: 520-522. DOI: 10.1109/Led.2009.2014975  0.352
2009 Liu F, Zhang L, Zhang J, He J, Chan M. Effects of body doping on threshold voltage and channel potential of symmetric DG MOSFETs with continuous solution from accumulation to strong-inversion regions Semiconductor Science and Technology. 24: 85005. DOI: 10.1088/0268-1242/24/8/085005  0.564
2009 He J, Zhang L, Zhang J, Ma C, Liu F, Chan M. A complete analytic surface potential-based core model for intrinsic nanowire surrounding-gate MOSFETs Molecular Simulation. 35: 483-490. DOI: 10.1080/08927020802706995  0.566
2009 He J, Zhang L, Zheng R, Zhang J, Chan M. A continuous surface-potential solution from accumulation to inversion for intrinsic symmetric double-gate MOSFETs Molecular Simulation. 35: 448-455. DOI: 10.1080/08927020802609454  0.547
2009 Samanta P, Cheng CL, Lee YJ, Chan M. Electrical stress-induced charge carrier generation/trapping related degradation of HfAlO/ SiO2 and HfO2 / SiO2 gate dielectric stacks Journal of Applied Physics. 105. DOI: 10.1063/1.3148297  0.391
2009 Liu F, Zhang J, He F, Liu F, Zhang L, Chan M. A charge-based compact model for predicting the current–voltage and capacitance–voltage characteristics of heavily doped cylindrical surrounding-gate MOSFETs Solid-State Electronics. 53: 49-53. DOI: 10.1016/J.Sse.2008.09.016  0.556
2009 Bian W, He J, Zhang L, Zhang J, Chan M. Sub-threshold behavior of long channel undoped cylindrical surrounding-gate MOSFETs Microelectronics Reliability. 49: 897-903. DOI: 10.1016/J.Microrel.2009.05.008  0.573
2009 Samanta P, Cheng CL, Lee YJ, Chan M. Mechanism of positive charge generation in the bulk of HfAlO/SiO2 stack Microelectronic Engineering. 86: 1767-1770. DOI: 10.1016/J.Mee.2009.03.002  0.353
2008 Liu F, He J, Zhang L, Zhang J, Hu J, Ma C, Chan M. A Charge-Based Model for Long-Channel Cylindrical Surrounding-Gate MOSFETs From Intrinsic Channel to Heavily Doped Body Ieee Transactions On Electron Devices. 55: 2187-2194. DOI: 10.1109/Ted.2008.926735  0.572
2008 Liu F, He J, Zhang J, Chen Y, Chan M. A Non-Charge-Sheet Analytic Model for Symmetric Double-Gate MOSFETs With Smooth Transition Between Partially and Fully Depleted Operation Modes Ieee Transactions On Electron Devices. 55: 3494-3502. DOI: 10.1109/Ted.2008.2006544  0.423
2008 Yang J, He J, Liu F, Zhang L, Liu F, Zhang X, Chan M. A Compact Model of Silicon-Based Nanowire MOSFETs for Circuit Simulation and Design Ieee Transactions On Electron Devices. 55: 2898-2906. DOI: 10.1109/Ted.2008.2005184  0.613
2008 Liu F, He J, Fu Y, Hu J, Bian W, Song Y, Zhang X, Chan M. Generic Carrier-Based Core Model for Undoped Four-Terminal Double-Gate MOSFETs Valid for Symmetric, Asymmetric, and Independent-Gate-Operation Modes Ieee Transactions On Electron Devices. 55: 816-826. DOI: 10.1109/Ted.2007.914836  0.427
2008 Man TY, Leung KN, Leung CY, Mok PKT, Chan M. Development of single-transistor-control LDO based on flipped voltage follower for SoC Ieee Transactions On Circuits and Systems I: Regular Papers. 55: 1392-1401. DOI: 10.1109/Tcsi.2008.916568  0.369
2008 Man TY, Mok PKT, Chan MJ. A 0.9-V input discontinuous-conduction-mode boost converter with CMOS-control rectifier Ieee Journal of Solid-State Circuits. 43: 2036-2046. DOI: 10.1109/Jssc.2008.2001933  0.348
2008 Ma C, Li B, Wei Y, Zhang L, He J, Zhang X, Lin X, Chan M. FinFET reliability study by forward gated-diode generation–recombination current Semiconductor Science and Technology. 23: 75008. DOI: 10.1088/0268-1242/23/7/075008  0.626
2008 He J, Bian W, Chen Y, Wei Y, Zhang L, Zhang J, Chan M. A rigorous carrier-based analytic model for undoped ultra-thin-body silicon-on-insulator (UTB-SOI) MOSFETs Molecular Simulation. 34: 63-72. DOI: 10.1080/08927020701730393  0.604
2008 Gong J, Chan PCH, Chan M. An explicit surface-potential-based model for undoped double-gate MOSFETs Solid-State Electronics. 52: 282-288. DOI: 10.1016/J.Sse.2007.08.013  0.375
2008 Wu D, Huang R, Bu W, Zhou F, Tian Y, Chen B, Feng C, Chan M, Wang Y. A novel source/drain on void (SDOV) MOSFET implemented by local co-implantation of hydrogen and helium Microelectronic Engineering. 85: 1490-1494. DOI: 10.1016/J.Mee.2008.01.079  0.396
2007 Tian Y, Xiao H, Huang R, Feng C, Chan M, Chen B, Wang R, Zhang X, Wang Y. Quasi-SOI MOSFETs—A Promising Bulk Device Candidate for Extremely Scaled Era Ieee Transactions On Electron Devices. 54: 1784-1788. DOI: 10.1109/Ted.2007.899401  0.4
2007 He J, Liu F, Zhang J, Feng J, Hu J, Yang S, Chan M. A Carrier-Based Approach for Compact Modeling of the Long-Channel Undoped Symmetric Double-Gate MOSFETs Ieee Transactions On Electron Devices. 54: 1203-1209. DOI: 10.1109/Ted.2007.893812  0.463
2007 Wu W, Chan M. Analysis of Geometry-Dependent Parasitics in Multifin Double-Gate FinFETs Ieee Transactions On Electron Devices. 54: 692-698. DOI: 10.1109/Ted.2007.891252  0.388
2007 He J, Bian W, Tao Y, Liu F, Song Y, Hu J, Zhang X, Wu W, Wang T, Chan M. Linear Cofactor Difference Extrema of MOSFET's Drain–Current and Application to Parameter Extraction Ieee Transactions On Electron Devices. 54: 874-878. DOI: 10.1109/Ted.2007.891249  0.384
2007 Man TY, Mok PKT, Chan M. A high slew-rate push-pull output amplifier for low-quiescent current low-dropout regulators with transient-response improvement Ieee Transactions On Circuits and Systems Ii: Express Briefs. 54: 755-759. DOI: 10.1109/Tcsii.2007.900347  0.34
2007 He J, Zhang L, Zhang J, Fu Y, Zheng R, Chan M. A unified carrier-based model for undoped symmetric double-gate and surrounding-gate MOSFETs Semiconductor Science and Technology. 22: 1312-1316. DOI: 10.1088/0268-1242/22/12/013  0.578
2007 He J, Bian W, Tao Y, Liu F, Lu K, Wu W, Wang T, Chan M. Corrigendum to “An explicit current–voltage model for undoped double-gate MOSFETs based on accurate yet analytic approximation to the carrier concentration” [Solid-State Electron. 51 (2007) 179–185] Solid-State Electronics. 51: 816. DOI: 10.1016/J.Sse.2007.03.003  0.342
2007 He J, Xi X, Wan H, Dunga M, Chan M, Niknejad AM. BSIM5: An advanced charge-based MOSFET model for nanoscale VLSI circuit simulation Solid-State Electronics. 51: 433-444. DOI: 10.1016/J.Sse.2006.12.006  0.44
2007 He J, Bian W, Tao Y, Liu F, Lu K, Wu W, Wang T, Chan M. An explicit current–voltage model for undoped double-gate MOSFETs based on accurate yet analytic approximation to the carrier concentration Solid-State Electronics. 51: 179-185. DOI: 10.1016/J.Sse.2006.11.010  0.354
2007 Samanta P, Zhu C, Chan M. Charge carrier generation/trapping mechanisms in HfO2/SiO2 stack Microelectronic Engineering. 84: 1964-1967. DOI: 10.1016/J.Mee.2007.04.084  0.358
2006 He J, Chan M, Zhang X, Wang Y. Erratum for "A Physics-Based Analytic Solution to the MOSFET Surface Potential From Accumulation to Strong-Inversion Region" Ieee Transactions On Electron Devices. 53: 2008-2016. DOI: 10.1109/Ted.2006.890468  0.322
2006 He J, Chan M, Zhang X, Wang Y. An Analytic Model to Account for Quantum–Mechanical Effects of MOSFETs Using a Parabolic Potential Well Approximation Ieee Transactions On Electron Devices. 53: 2082-2090. DOI: 10.1109/Ted.2006.880359  0.308
2006 Lin X, Zhang S, Wu X, Chan M. Local clustering 3-D stacked CMOS technology for interconnect loading reduction Ieee Transactions On Electron Devices. 53: 1405-1410. DOI: 10.1109/Ted.2006.873847  0.3
2006 Wu W, Lam S, Chan M. A wide-band T/R switch using enhanced compact Waffle MOSFETs Ieee Microwave and Wireless Components Letters. 16: 287-289. DOI: 10.1109/Lmwc.2006.873495  0.338
2006 Wu W, Chan M. Gate resistance modeling of multifin MOS devices Ieee Electron Device Letters. 27: 68-70. DOI: 10.1109/Led.2005.861599  0.364
2006 Samanta P, Man TY, Chan ACK, Zhang Q, Zhu C, Chan M. Experimental evidence of two conduction mechanisms for direct tunnelling stress-induced leakage current through ultrathin silicon dioxide gate dielectrics Semiconductor Science and Technology. 21: 1393-1401. DOI: 10.1088/0268-1242/21/10/004  0.367
2006 Samanta P, Man TY, Zhang Q, Zhu C, Chan M. Direct tunneling stress-induced leakage current in ultrathin HfO 2SiO2 gate dielectric stacks Journal of Applied Physics. 100. DOI: 10.1063/1.2372313  0.331
2006 Sen B, Wong H, Filip V, Choi HY, Sarkar CK, Chan M, Kok CW, Poon MC. Current transport and high-field reliability of aluminum/hafnium oxide/silicon structure Thin Solid Films. 504: 312-316. DOI: 10.1016/J.Tsf.2005.09.052  0.358
2006 Choi HY, Wong H, Filip V, Sen B, Kok CW, Chan M, Poon MC. Stressing effects on the charge trapping of silicon oxynitride prepared by thermal oxidation of LPCVD Si-rich silicon nitride Thin Solid Films. 504: 7-10. DOI: 10.1016/J.Tsf.2005.09.018  0.333
2006 He J, Chan M, Zhang X, Wang Y. A new analytic method to design multiple floating field limiting rings of power devices Solid-State Electronics. 50: 1375-1381. DOI: 10.1016/J.Sse.2006.06.012  0.339
2006 He J, Zhang X, Zhang G, Chan M, Wang Y. A carrier-based analytic DCIV model for long channel undoped cylindrical surrounding-gate MOSFETs Solid-State Electronics. 50: 416-421. DOI: 10.1016/J.Sse.2006.01.015  0.458
2006 Sen B, Sarkar CK, Wong H, Chan M, Kok CW. Electrical characteristics of high-κ dielectric film grown by direct sputtering method Solid-State Electronics. 50: 237-240. DOI: 10.1016/J.Sse.2005.11.010  0.332
2005 Lin X, Chan M. A highly scalable opposite side floating-gate flash memory cell Ieee Transactions On Electron Devices. 52: 2042-2045. DOI: 10.1109/Ted.2005.855061  0.359
2005 Wu X, Chan PCH, Zhang S, Feng C, Chan M. A three-dimensional stacked fin-CMOS technology for high-density ULSI circuits Ieee Transactions On Electron Devices. 52: 1998-2003. DOI: 10.1109/Ted.2005.854267  0.375
2005 Chan ACK, Cheng CF, Chan M. Effects of dopants on the electrical behavior of grain boundary in metal-induced crystallized polysilicon film Ieee Transactions On Electron Devices. 52: 1917-1919. DOI: 10.1109/Ted.2005.852735  0.353
2005 Xu C, Shen C, Wu W, Chan M. Backside-illuminated lateral PIN photodiode for CMOS image sensor on SOS substrate Ieee Transactions On Electron Devices. 52: 1110-1115. DOI: 10.1109/Ted.2005.848106  0.312
2005 Wu X, Chan PCH, Chan M. Impacts of nonrectangular fin cross section on the electrical characteristics of FinFET Ieee Transactions On Electron Devices. 52: 63-68. DOI: 10.1109/Ted.2004.841334  0.364
2005 Leung CY, Mok PKT, Leung KN, Chan M. An integrated CMOS current-sensing circuit for low-Voltage current-mode buck regulator Ieee Transactions On Circuits and Systems Ii-Express Briefs. 52: 394-397. DOI: 10.1109/Tcsii.2005.850403  0.361
2005 Wu X, Chan PCH, Zhang S, Feng C, Chan M. Stacked 3-D Fin-CMOS technology Ieee Electron Device Letters. 26: 416-418. DOI: 10.1109/Led.2005.848070  0.335
2005 Yin C, Chan PCH, Chan M. An air spacer technology for improving short-channel immunity of MOSFETs with raised source/drain and high-/spl kappa/ gate dielectric Ieee Electron Device Letters. 26: 323-325. DOI: 10.1109/Led.2005.846584  0.384
2005 Lee W, Ng AFL, Tang JJ, Chan M. Compact modeling of transient substrate current of MOSFET Solid-State Electronics. 49: 1405-1409. DOI: 10.1016/J.Sse.2005.06.009  0.374
2005 Man TY, Chan M. A 2-bit highly scalable nonvolatile memory cell with two electrically isolated charge trapping sites Microelectronics Reliability. 45: 349-354. DOI: 10.1016/J.Microrel.2004.08.016  0.333
2004 Lam S, Lee W, Chan AC-, Mok PKT, Ko PK, Chan M. A Workable Use of the Floating-Body Silicon-On-Sapphire MOSFET as a Transconductance Mixer Japanese Journal of Applied Physics. 43: 2176-2179. DOI: 10.1143/Jjap.43.2176  0.377
2004 Chan ACK, Man TY, He J, Yuen KH, Lee WK, Chan M. SOI flash memory scaling limit and design consideration based on 2-D analytical modeling Ieee Transactions On Electron Devices. 51: 2054-2060. DOI: 10.1109/Ted.2004.838327  0.421
2004 Cheng CF, Jagar S, Poon MC, Kok CW, Chan M. A statistical model to predict the performance variation of polysilicon TFTs formed by grain-enhancement technology Ieee Transactions On Electron Devices. 51: 2061-2068. DOI: 10.1109/Ted.2004.838325  0.357
2004 Cheng CF, Leung TC, Poon MC, Kok CW, Chan M. Modeling of large-grain polysilicon formation under retardation effect of SPC Ieee Transactions On Electron Devices. 51: 2205-2210. DOI: 10.1109/Ted.2004.838323  0.325
2004 Zhang Z, Zhang S, Feng C, Chan M. Analysis and optimization of SDOI structure to maximize the intrinsic performance of extremely scaled MOSFETs Ieee Transactions On Electron Devices. 51: 1095-1100. DOI: 10.1109/Ted.2004.829515  0.515
2004 Zhang Z, Zhang S, Chan M. Self-align recessed source drain ultrathin body SOI MOSFET Ieee Electron Device Letters. 25: 740-742. DOI: 10.1109/Led.2004.837582  0.503
2004 Zhang S, Han R, Lin X, Wu X, Chan M. A stacked CMOS technology on SOI substrate Ieee Electron Device Letters. 25: 661-663. DOI: 10.1109/Led.2004.834735  0.562
2003 Zhang S, Lin X, Huang R, Han R, Chan M. A self-aligned, electrically separable double-gate MOS transistor technology for dynamic threshold voltage application Ieee Transactions On Electron Devices. 50: 2297-2300. DOI: 10.1109/Ted.2003.818598  0.583
2003 Li J, Xue M, Lu Z, Zhang Z, Feng C, Chan M. A high-density conduction-based micro-DNA identification array fabricated with a CMOS compatible process Ieee Transactions On Electron Devices. 50: 2165-2170. DOI: 10.1109/Ted.2003.816545  0.478
2003 Zhang S, Chan ACK, Han R, Huang R, Liu X, Wang Y, Ko PK, Chan M. A viable self-aligned bottom-gate MOS transistor technology for deep submicron 3-D SRAM Ieee Transactions On Electron Devices. 50: 1952-1960. DOI: 10.1109/Ted.2003.815859  0.444
2003 Cheng CF, Poon VMC, Kok CW, Chan M. Modeling of grain growth mechanism by nickel silicide reactive grain boundary effect in metal-induced-lateral-crystallization Ieee Transactions On Electron Devices. 50: 1467-1474. DOI: 10.1109/Ted.2003.813521  0.306
2003 Jagar S, Cheng CF, Zhang S, Wang H, Poon MC, Kok CW, Chan M. A SPICE model for thin-film transistors fabricated on grain-enhanced polysilicon film Ieee Transactions On Electron Devices. 50: 1103-1108. DOI: 10.1109/Ted.2003.812487  0.388
2003 Yuen KH, Man TY, Chan ACK, Chan M. A 2-bit MONOS nonvolatile memory cell based on asymmetric double gate MOSFET structure Ieee Electron Device Letters. 24: 518-520. DOI: 10.1109/Led.2003.815157  0.376
2003 Lam S, Wan H, Su P, Wyatt PW, Chen CL, Niknejad AM, Hu C, Ko PK, Chan M. RF characterization of metal T-gate structure in fully-depleted SOI CMOS technology Ieee Electron Device Letters. 24: 251-253. DOI: 10.1109/Led.2003.810892  0.332
2003 Chan AC-, Chan M. Effects of floating body on double polysilicon partially depleted SOI nonvolatile memory cell Ieee Electron Device Letters. 24: 75-77. DOI: 10.1109/Led.2003.808840  0.392
2003 Su P, Fung SKH, Wyatt PW, Wan H, Niknejad AM, Chan M, Hu C. On the body-source built-in potential lowering of SOI MOSFETs Ieee Electron Device Letters. 24: 90-92. DOI: 10.1109/Led.2002.807696  0.346
2003 Ying T, Ki WH, Chan M. Area-Efficient CMOS Charge Pumps for LCD Drivers Ieee Journal of Solid-State Circuits. 38: 1721-1725. DOI: 10.1109/Jssc.2003.817596  0.353
2003 Cheung VS-, Luong HC, Chan M, Ki W. A 1-V 3.5-mW CMOS switched-opamp quadrature IF circuitry for Bluetooth receivers Ieee Journal of Solid-State Circuits. 38: 805-816. DOI: 10.1109/Jssc.2003.810031  0.313
2002 Ng KL, Zhan N, Poon MC, Kok CW, Chan M, Wong H. High Quality HfO 2 Film and Its Applications in Novel Poly-Si Devices Mrs Proceedings. 716: 91. DOI: 10.1557/Proc-716-B2.6  0.303
2002 Zhang S, Han R, Sin JKO, Chan M. Reduction of off-current in self-aligned double-gate TFT with mask-free symmetric LDD Ieee Transactions On Electron Devices. 49: 1490-1492. DOI: 10.1109/Ted.2002.801232  0.383
2002 He J, Xi X, Chan M, Hu C, Li Y, Zhang X, Huang R, Wang Y. Equivalent junction method to predict 3-D effect of curved-abrupt p-n junctions Ieee Transactions On Electron Devices. 49: 1322-1325. DOI: 10.1109/Ted.2002.1013296  0.39
2002 Zhang S, Han R, Zhang Z, Huang R, Ko PK, Chan M. Implementation of fully self-aligned bottom-gate MOS transistor Ieee Electron Device Letters. 23: 618-620. DOI: 10.1109/Led.2002.803763  0.526
2002 He J, Xi X, Chan M, Cao K, Hu C, Li Y, Zhang X, Huang R, Wang Y. Normalized mutual integral difference method to extract threshold voltage of MOSFETs Ieee Electron Device Letters. 23: 428-430. DOI: 10.1109/Led.2002.1015230  0.345
2002 Xu C, Ki W, Chan M. A low-voltage CMOS complementary active pixel sensor (CAPS) fabricated using a 0.25 μm CMOS technology Ieee Electron Device Letters. 23: 398-400. DOI: 10.1109/Led.2002.1015213  0.331
2002 Xu C, Zhang W, Ki W, Chan M. A 1.0-V V/sub DD/ CMOS active-pixel sensor with complementary pixel architecture and pulsewidth modulation fabricated with a 0.25-/spl mu/m CMOS process Ieee Journal of Solid-State Circuits. 37: 1853-1859. DOI: 10.1109/Jssc.2002.804346  0.571
2002 Ng AF-, Ko PK, Chan M. Determining the onset frequency of nonquasistatic effects of the MOSFET in AC simulation Ieee Electron Device Letters. 23: 37-39. DOI: 10.1109/55.974805  0.319
2002 He J, Wang Y, Zhang X, Xi X, Chan M, Huang R, Hu C. A simple method for optimization of 6H-SiC punch-through junctions used in both unipolar and bipolar power devices Ieee Transactions On Electron Devices. 49: 933-937. DOI: 10.1109/16.998606  0.332
2002 Jagar S, Wang H, Chan M. Design methodology of the high performance large-grain polysilicon MOSFET Ieee Transactions On Electron Devices. 49: 795-801. DOI: 10.1109/16.998586  0.31
2002 Zhang S, Han R, Sin JKO, Chan M. Implementation and characterization of self-aligned double-gate TFT with thin channel and thick source/drain Ieee Transactions On Electron Devices. 49: 718-724. DOI: 10.1109/16.998576  0.436
2001 Lin X, Feng C, Zhang S, Ho W, Chan M. A Simple Method to Fabricate Double-Gate SOI MOSFET with Diffusion Layer on Bulk Silicon Wafer as the Bottom Gate The Japan Society of Applied Physics. 2001: 252-253. DOI: 10.7567/Ssdm.2001.C-4-4  0.352
2001 Shivani S, Ng KL, Cheng CF, Poon MC, Chan M. Effects of process conditions on the performance of large grain poly-silicon on insulator (LPSOI) MOSFET for advanced CMOS applications Mrs Proceedings. 686: 127. DOI: 10.1557/Proc-686-A4.3  0.332
2001 Zhang S, Han R, Sin JKO, Chan M. A novel self-aligned double-gate TFT technology Ieee Electron Device Letters. 22: 530-532. DOI: 10.1109/55.962653  0.426
2001 Ng AF-, Lee W, Ko PK, Chan M. MOSFET drain/source charge partition under nonquasi-static switching Ieee Electron Device Letters. 22: 484-486. DOI: 10.1109/55.954919  0.415
2001 Zhang S, Han R, Chan MJ. A novel self-aligned bottom gate poly-Si TFT with in-situ LDD Ieee Electron Device Letters. 22: 393-395. DOI: 10.1109/55.936354  0.42
2001 Chan ACK, Wang H, Chan MJ. High quality thermal oxide on LPSOI formed by high temperature enhanced MILC Ieee Electron Device Letters. 22: 384-386. DOI: 10.1109/55.936351  0.351
2001 Xu C, Zhang W, Chan M. A low voltage hybrid bulk/SOI CMOS active pixel image sensor Ieee Electron Device Letters. 22: 248-250. DOI: 10.1109/55.919244  0.597
2001 Jagar S, Wang H, Chan M. Effects of longitudinal and latitudinal grain boundaries on the performance of large-grain polysilicon MOSFET Ieee Electron Device Letters. 22: 218-220. DOI: 10.1109/55.919234  0.375
2001 Chan VWC, Chan PCH, Chan M. Multiple layers of CMOS integrated circuits using recrystallized silicon film Ieee Electron Device Letters. 22: 77-79. DOI: 10.1109/55.902837  0.415
2001 Wang H, Singh J, Lam S, Chan M. High frequency performance of large-grain polysilicon-on-insulator MOSFETs Ieee Transactions On Electron Devices. 48: 1480-1482. DOI: 10.1109/16.930672  0.329
2001 Chan VWC, Chan PCH, Chan M. Three-dimensional CMOS SOI integrated circuit using high-temperature metal-induced lateral crystallization Ieee Transactions On Electron Devices. 48: 1394-1399. DOI: 10.1109/16.930657  0.412
2001 Zhang W, Chan M. A high gain n-well/gate tied PMOSFET image sensor fabricated from a standard CMOS process Ieee Transactions On Electron Devices. 48: 1097-1102. DOI: 10.1109/16.925233  0.597
2001 Chan M, Ko PK. Development of a viable 3D integrated circuit technology Science in China Series F: Information Sciences. 44: 241-248. DOI: 10.1007/Bf02714712  0.332
2000 Shivani S, Poon MC, Chan M, Ko PK. Effect of Ramp Annealing to Ni Induced Lateral Crystallization of Amorphous Silicon Mrs Proceedings. 609. DOI: 10.1557/Proc-609-A9.7  0.32
2000 Chan WY, Myasnikov AM, Poon MC, Yuen CY, Han PG, Chan M, Ko PK. Effect Of Nickel In Large Grain Poly-Si Film Formed By Nickel Induced Lateral Crystallization and New Grain Enhancement Method Mrs Proceedings. 609. DOI: 10.1557/Proc-609-A31.6  0.32
2000 Wang H, Chan M, Jagar S, Wang Y, Ko PK. Submicron super TFTs for 3-D VLSI applications Ieee Electron Device Letters. 21: 439-441. DOI: 10.1109/55.863104  0.369
2000 Wang H, Chan M, Jagar S, Poon VMC, Qin M, Wang Y, Ko PK. Super thin-film transistor with SOI CMOS performance formed by a novel grain enhancement method Ieee Transactions On Electron Devices. 47: 1580-1586. DOI: 10.1109/16.853034  0.387
2000 Zhang W, Chan M, Ko PK. Performance of the floating gate/body tied NMOSFET photodetector on SOI substrate Ieee Transactions On Electron Devices. 47: 1375-1384. DOI: 10.1109/16.848280  0.615
2000 Wang H, Chan M, Wang Y, Ko PK. The behavior of narrow-width SOI MOSFETs with MESA isolation Ieee Transactions On Electron Devices. 47: 593-600. DOI: 10.1109/16.824735  0.426
2000 Zhang W, Chan M, Huang R, Ko PK. High gain gate/body tied NMOSFET photo-detector on SOI substrate for low power applications Solid-State Electronics. 44: 535-540. DOI: 10.1016/S0038-1101(99)00260-9  0.609
1999 Banna SR, Chan PCH, Chan M, Fung SKH, Ko PK. Fully depleted CMOS/SOI device design guidelines for low-power applications Ieee Transactions On Electron Devices. 46: 754-761. DOI: 10.1109/16.753710  0.378
1998 Zhang W, Chan M, Fung SKH, Ko PK. Performance of a CMOS compatible lateral bipolar photodetector on SOI substrate Ieee Electron Device Letters. 19: 435-437. DOI: 10.1109/55.728904  0.605
1998 Jin W, Chan CH, Chan M. On the power dissipation in dynamic threshold silicon-on-insulator CMOS inverter Ieee Transactions On Electron Devices. 45: 1717-1724. DOI: 10.1109/16.704370  0.352
1998 Fung SKH, Chan M, Ko PK. Impact of scaling silicon film thickness and channel width on SOI MOSFET with reoxidized MESA isolation Ieee Transactions On Electron Devices. 45: 1105-1110. DOI: 10.1109/16.669545  0.382
1998 Chan M, Hui KY, Hu C, Ko PK. A robust and physical BSIM3 non-quasi-static transient and AC small-signal model for circuit simulation Ieee Transactions On Electron Devices. 45: 834-841. DOI: 10.1109/16.662788  0.404
1998 Banna SR, Chan CH, Chan M, Fung SKH, Ko PK. A unified understanding on fully-depleted SOI NMOSFET hot-carrier degradation Ieee Transactions On Electron Devices. 45: 206-212. DOI: 10.1109/16.658832  0.389
1998 Poon M, Chan M, Zhang W, Deng F, Lau S. Stability of NiSi in boron-doped polysilicon lines Microelectronics Reliability. 38: 1499-1502. DOI: 10.1016/S0026-2714(98)00046-8  0.31
1997 Sinitsky D, Tu R, Liang C, Chan M, Bokor J, Hu C. AC output conductance of SOI MOSFETs and impact on analog applications Ieee Electron Device Letters. 18: 36-38. DOI: 10.1109/55.553036  0.347
1997 Cheng Y, Jeng M, Liu Z, Huang J, Chan M, Chen K, Ko PK, Hu C. A physical and scalable I-V model in BSIM3v3 for analog/digital circuit simulation Ieee Transactions On Electron Devices. 44: 277-287. DOI: 10.1109/16.557715  0.458
1997 Fung SKH, Chan M, Ko PK. Inverse-narrow-width effect of deep sub-micrometer MOSFETs with LOCOS isolation Solid-State Electronics. 41: 1885-1889. DOI: 10.1016/S0038-1101(97)00166-4  0.418
1996 Banna SR, Chan PCH, Chan M, Ko PK. A physically based compact device model for fully depleted and nearly fully depleted SOI MOSFET Ieee Transactions On Electron Devices. 43: 1914-1923. DOI: 10.1109/16.543027  0.41
1995 Chan M, King JC, Ko PK, Hu C. SOI/bulk hybrid technology on SIMOX wafers for high performance circuits with good ESD immunity Ieee Electron Device Letters. 16: 11-13. DOI: 10.1109/55.363215  0.374
1995 Chan M, Yu B, Ma Z, Nguyen CT, Hu C, Ko PK. Comparative study of fully depleted and body-grounded non fully depleted SOI MOSFETs for high performance analog and mixed signal circuits Ieee Transactions On Electron Devices. 42: 1975-1981. DOI: 10.1109/16.469406  0.395
1995 Banna SR, Chan PCH, Ko PK, Nguyen CT, Chan M. Threshold voltage model for deep-submicrometer fully depleted SOI MOSFET's Ieee Transactions On Electron Devices. 42: 1949-1955. DOI: 10.1109/16.469402  0.413
1995 Chan M, Yuen SS, Ma Z, Hui KY, Ko PK, Hu C. ESD reliability and protection schemes in SOI CMOS output buffers Ieee Transactions On Electron Devices. 42: 1816-1821. DOI: 10.1109/16.464414  0.38
1994 Chan M, Assaderaghi F, Hu C, Ko PK, Parke SA. Recessed-Channel Structure for Fabricating Ultrathin SOI MOSFET with Low Series Resistance Ieee Electron Device Letters. 15: 22-24. DOI: 10.1109/55.289474  0.375
1994 Ma ZJ, Wann HJ, Chan M, King JC, Cheng YC, Ko PK, Hu C. Hot-carrier effects in thin-film fully depleted SOI MOSFET's Ieee Electron Device Letters. 15: 218-220. DOI: 10.1109/55.286697  0.356
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