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Tinoosh Mohsenin, Ph.D. - Publications

Affiliations: 
2010 Electrical and Computer Engineering University of California, Davis, Davis, CA 
Area:
Electronics and Electrical Engineering, Computer Engineering
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48 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2019 Shea C, Mohsenin T. Heterogeneous Scheduling of Deep Neural Networks for Low-power Real-time Designs Acm Journal On Emerging Technologies in Computing Systems. 15: 1-31. DOI: 10.1145/3358699  0.352
2019 Jafari A, Ganesan A, Thalisetty CSK, Sivasubramanian V, Oates T, Mohsenin T. SensorNet: A Scalable and Low-Power Deep Convolutional Neural Network for Multimodal Data Classification Ieee Transactions On Circuits and Systems I: Regular Papers. 66: 274-287. DOI: 10.1109/Tcsi.2018.2848647  0.49
2019 Malik M, Neshatpour K, Rafatirad S, Joshi RV, Mohsenin T, Ghasemzadeh H, Homayoun H. Big vs little core for energy-efficient Hadoop computing Journal of Parallel and Distributed Computing. 129: 110-124. DOI: 10.1016/J.Jpdc.2018.02.017  0.472
2018 Jafari A, Buswell N, Ghovanloo M, Mohsenin T. A Low-Power Wearable Stand-Alone Tongue Drive System for People With Severe Disabilities. Ieee Transactions On Biomedical Circuits and Systems. 12: 58-67. PMID 29377796 DOI: 10.1109/Tbcas.2017.2757031  0.443
2018 Hajkazemi MH, Tavana MK, Mohsenin T, Homayoun H. Heterogeneous HMC+DDRx Memory Management for Performance-Temperature Tradeoffs Acm Journal On Emerging Technologies in Computing Systems. 14: 1-21. DOI: 10.1145/3106233  0.351
2018 Kulkarni A, Shea C, Abtahi T, Homayoun H, Mohsenin T. Low Overhead CS-Based Heterogeneous Framework for Big Data Acceleration Acm Transactions On Embedded Computing Systems. 17: 1-25. DOI: 10.1145/3092944  0.484
2018 Abtahi T, Shea C, Kulkarni A, Mohsenin T. Accelerating Convolutional Neural Network With FFT on Embedded Hardware Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 26: 1737-1749. DOI: 10.1109/Tvlsi.2018.2825145  0.46
2018 Kulkarni A, Page A, Attaran N, Jafari A, Malik M, Homayoun H, Mohsenin T. An Energy-Efficient Programmable Manycore Accelerator for Personalized Biomedical Applications Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 26: 96-109. DOI: 10.1109/Tvlsi.2017.2754272  0.488
2018 Attaran N, Puranik A, Brooks J, Mohsenin T. Embedded Low-Power Processor for Personalized Stress Detection Ieee Transactions On Circuits and Systems Ii: Express Briefs. 65: 2032-2036. DOI: 10.1109/Tcsii.2018.2799821  0.474
2018 Neshatpour K, Malik M, Sasan A, Rafatirad S, Mohsenin T, Ghasemzadeh H, Homayoun H. Energy-efficient acceleration of MapReduce applications using FPGAs Journal of Parallel and Distributed Computing. 119: 1-17. DOI: 10.1016/J.Jpdc.2018.02.004  0.374
2017 Page A, Jafari A, Shea C, Mohsenin T. SPARCNet Acm Journal On Emerging Technologies in Computing Systems. 13: 1-32. DOI: 10.1145/3005448  0.446
2017 Kulkarni A, Mohsenin T. Low Overhead Architectures for OMP Compressive Sensing Reconstruction Algorithm Ieee Transactions On Circuits and Systems I: Regular Papers. 64: 1468-1480. DOI: 10.1109/Tcsi.2017.2648854  0.473
2016 Kulkarni A, Abtahi T, Smith E, Mohsenin T. Low energy sketching engines on many-core platform for big data acceleration Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 18: 57-62. DOI: 10.1145/2902961.2902984  0.396
2016 Kulkarni A, Pino Y, French M, Mohsenin T. Real-time anomaly detection framework for many-core router through machine-learning techniques Acm Journal On Emerging Technologies in Computing Systems. 13. DOI: 10.1145/2827699  0.399
2016 Kulkarni A, Jafari A, Sagedy C, Mohsenin T. Sketching-based high-performance biomedical big data processing accelerator Proceedings - Ieee International Symposium On Circuits and Systems. 2016: 1138-1141. DOI: 10.1109/ISCAS.2016.7527446  0.303
2016 Truong D, Cheng W, Mohsenin T, Yu Z, Jacobson T, Landge G, Meeuwsen M, Watnik C, Mejia P, Tran A, Webb J, Work E, Xiao Z, Baas B. A 167-processor computational array for highly-efficient DSP and embedded application processing 2008 Ieee Hot Chips 20 Symposium, Hcs 2008. DOI: 10.1109/HOTCHIPS.2008.7476535  0.353
2015 Viseh S, Ghovanloo M, Mohsenin T. Toward an Ultralow-Power Onboard Processor for Tongue Drive System. Ieee Transactions On Circuits and Systems. Ii, Express Briefs : a Publication of the Ieee Circuits and Systems Society. 62: 174-178. PMID 26185489 DOI: 10.1109/Tcsii.2014.2387683  0.482
2015 Page A, Sagedy C, Smith E, Attaran N, Oates T, Mohsenin T. A flexible multichannel EEG feature extractor and classifier for seizure detection Ieee Transactions On Circuits and Systems Ii: Express Briefs. 62: 109-113. DOI: 10.1109/Tcsii.2014.2385211  0.343
2015 Kulkarni A, Mohsenin T. Accelerating compressive sensing reconstruction OMP algorithm with CPU, GPU, FPGA and domain specific many-core Proceedings - Ieee International Symposium On Circuits and Systems. 2015: 970-973. DOI: 10.1109/ISCAS.2015.7168797  0.348
2015 Jafari A, Page A, Sagedy C, Smith E, Mohsenin T. A low power seizure detection processor based on direct use of compressively-sensed data and employing a deterministic random matrix Ieee Biomedical Circuits and Systems Conference: Engineering For Healthy Minds and Able Bodies, Biocas 2015 - Proceedings. DOI: 10.1109/BioCAS.2015.7348376  0.315
2015 Page A, Kulkarni A, Mohsenin T. Utilizing deep neural nets for an embedded ECG-based biometric authentication system Ieee Biomedical Circuits and Systems Conference: Engineering For Healthy Minds and Able Bodies, Biocas 2015 - Proceedings. DOI: 10.1109/BioCAS.2015.7348372  0.322
2015 Jafari A, Buswell N, Page A, Mohsenin T, Sahadat MN, Ghovanloo M. Live demonstration: Towards an ultra low power on-board processor for Tongue Drive System Ieee Biomedical Circuits and Systems Conference: Engineering For Healthy Minds and Able Bodies, Biocas 2015 - Proceedings. DOI: 10.1109/BioCAS.2015.7348332  0.315
2014 Ashammagari AR, Mahmoodi H, Mohsenin T, Homayoun H. Reconfigurable STT-NV LUT-based functional units to improve performance in general-purpose processors Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 249-254. DOI: 10.1145/2591513.2591535  0.329
2014 Kulkarni A, Stanislaus JLVM, Mohsenin T. Parallel heterogeneous architectures for efficient OMP compressive sensing reconstruction Proceedings of Spie - the International Society For Optical Engineering. 9109. DOI: 10.1117/12.2050530  0.479
2013 Mohsenin T, Shirani-Mehr H, Baas BM. LDPC decoder with an adaptive wordwidth datapath for energy and BER co-optimization Vlsi Design. 2013. DOI: 10.1155/2013/913018  0.714
2013 Korde A, Bradley D, Mohsenin T. Detection performance of radar compressive sensing in noisy environments Proceedings of Spie. 8717. DOI: 10.1117/12.2016209  0.32
2013 Bisasky J, Homayoun H, Yazdani F, Mohsenin T. A 64-core platform for biomedical signal processing Proceedings - International Symposium On Quality Electronic Design, Isqed. 368-372. DOI: 10.1109/ISQED.2013.6523637  0.422
2013 Stanislaus JLVM, Mohsenin T. Low-complexity FPGA implementation of compressive sensing reconstruction 2013 International Conference On Computing, Networking and Communications, Icnc 2013. 671-675. DOI: 10.1109/ICCNC.2013.6504167  0.335
2013 Page A, Mohsenin T. An efficient & reconfigurable FPGA and ASIC implementation of a spectral Doppler ultrasound imaging system Proceedings of the International Conference On Application-Specific Systems, Architectures and Processors. 198-202. DOI: 10.1109/ASAP.2013.6567575  0.337
2012 Bisasky J, Chandler D, Mohsenin T. A many-core platform implemented for multi-channel seizure detection Iscas 2012 - 2012 Ieee International Symposium On Circuits and Systems. 564-567. DOI: 10.1109/ISCAS.2012.6272092  0.355
2012 Stanislaus JLVM, Mohsenin T. High performance compressive sensing reconstruction hardware with QRD process Iscas 2012 - 2012 Ieee International Symposium On Circuits and Systems. 29-32. DOI: 10.1109/ISCAS.2012.6271921  0.336
2011 Mohsenin T, Shirani-Mehr H, Baas B. Low power LDPC decoder with efficient stopping scheme for undecodable blocks Proceedings - Ieee International Symposium On Circuits and Systems. 1780-1783. DOI: 10.1109/ISCAS.2011.5937929  0.383
2011 Shirani-Mehr H, Mohsenin T, Baas B. A reduced routing network architecture for partial parallel LDPC decoders Conference Record - Asilomar Conference On Signals, Systems and Computers. 2192-2196. DOI: 10.1109/ACSSC.2011.6190420  0.393
2010 Mohsenin T, Truong DN, Baas BM. A low-complexity message-passing algorithm for reduced routing congestion in LDPC decoders Ieee Transactions On Circuits and Systems I: Regular Papers. 57: 1048-1061. DOI: 10.1109/Tcsi.2010.2046957  0.75
2010 Mohsenin T, Baas BM. A split-decoding message passing algorithm for low density parity check decoders Journal of Signal Processing Systems. 61: 329-345. DOI: 10.1007/s11265-010-0456-y  0.736
2009 Truong DN, Cheng WH, Mohsenin T, Yu Z, Jacobson AT, Landge G, Meeuwsen MJ, Watnik C, Tran AT, Xiao Z, Work EW, Webb JW, Mejia PV, Baas BM. A 167-processor computational platform in 65 nm CMOS Ieee Journal of Solid-State Circuits. 44: 1130-1144. DOI: 10.1109/Jssc.2009.2013772  0.743
2009 Mohsenin T, Truong D, Baas B. Multi-split-row threshold decoding implementations for LDPC codes Proceedings - Ieee International Symposium On Circuits and Systems. 2449-2452. DOI: 10.1109/ISCAS.2009.5118296  0.42
2009 Mohsenin T, Truong D, Baas B. An improved split-row threshold decoding algorithm for LDPC codes Ieee International Conference On Communications. DOI: 10.1109/ICC.2009.5198733  0.331
2009 Mohsenin T, Baas B. Trends and challenges in LDPC hardware decoders Conference Record - Asilomar Conference On Signals, Systems and Computers. 1273-1277. DOI: 10.1109/ACSSC.2009.5469947  0.43
2008 Truong D, Cheng W, Mohsenin T, Yu Z, Jacobson T, Landge G, Meeuwsen M, Watnik C, Mejia P, Tran A, Webb J, Work E, Xiao Z, Baas B. A 167-processor 65 nm computational platform with per-processor dynamic supply voltage and dynamic clock frequency scaling Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 22-23. DOI: 10.1109/VLSIC.2008.4585936  0.329
2008 Yu Z, Meeuwsen MJ, Apperson RW, Sattari O, Lai M, Webb JW, Work EW, Truong D, Mohsenin T, Baas BM. AsAP: An asynchronous array of simple processors Ieee Journal of Solid-State Circuits. 43: 695-705. DOI: 10.1109/Jssc.2007.916616  0.739
2008 Mohsenin T, Urard P, Baas B. A thresholding algorithm for improved split-row decoding of LDPC codes Conference Record - Asilomar Conference On Signals, Systems and Computers. 448-451. DOI: 10.1109/ACSSC.2008.5074444  0.327
2008 Yu Z, Meeuwsen MJ, Apperson RW, Sattari O, Lai MA, Webb JW, Work EW, Mohsenin T, Baas BM. Architecture and evaluation of an asynchronous array of simple processors Journal of Signal Processing Systems. 53: 243-259. DOI: 10.1007/s11265-008-0162-1  0.75
2007 Apperson RW, Yu Z, Meeuwsen MJ, Mohsenin T, Baas BM. A scalable dual-clock FIFO for data transfers between arbitrary and haltable clock domains Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 15: 1125-1134. DOI: 10.1109/Tvlsi.2007.903938  0.738
2007 Baas B, Yu Z, Meeuwsen M, Sattari O, Apperson R, Work E, Webb J, Lai M, Mohsenin T, Truong D, Cheung J. AsAP: A fine-grained many-core platform for DSP applications Ieee Micro. 27: 34-45. DOI: 10.1109/Mm.2007.29  0.742
2007 Mohsenin T, Baas BM. High-throughput LDPC decoders using a multiple split-row method Icassp, Ieee International Conference On Acoustics, Speech and Signal Processing - Proceedings. 2. DOI: 10.1109/ICASSP.2007.366160  0.64
2006 Mohsenin T, Baas BM. Split-row: A reduced complexity, high throughput LDPC decoder architecture Ieee International Conference On Computer Design, Iccd 2006. 320-325. DOI: 10.1109/ICCD.2006.4380835  0.708
2006 Yu Z, Meeuwsen M, Apperson R, Sattari O, Lai M, Webb J, Work E, Mohsenin T, Singh M, Baas B. An asynchronous array of simple processors for DSP applications Digest of Technical Papers - Ieee International Solid-State Circuits Conference.  0.514
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