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Zhichun Zhu - Publications

Affiliations: 
Electrical and Computer Engineering University of Illinois at Chicago, Chicago, IL, United States 
Area:
Computer Engineering
Website:
https://ece.uic.edu/profiles/zhichun-zhu-phd/
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7 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2019 Pourshirazi B, Beigi MV, Zhu Z, Memik G. Writeback-Aware LLC Management for PCM-Based Main Memory Systems Acm Transactions On Design Automation of Electronic Systems. 24: 18. DOI: 10.1145/3292009  0.331
2014 Fang K, Zheng H, Lin J, Zhang Z, Zhu Z. Mini-Rank: A Power-EfficientDDRx DRAM Memory Architecture Ieee Transactions On Computers. 63: 1500-1512. DOI: 10.1109/Tc.2012.240  0.337
2013 Lin J, Zheng H, Zhu Z, Zhang Z. Thermal Modeling and Management of DRAM Systems Ieee Transactions On Computers. 62: 2069-2082. DOI: 10.1109/Tc.2012.118  0.34
2010 Zheng H, Zhu Z. Power and Performance Trade-Offs in Contemporary DRAM System Designs for Multicore Processors Ieee Transactions On Computers. 59: 1033-1046. DOI: 10.1109/Tc.2010.108  0.325
2005 Zhu Z, Zhang X. Look-ahead architecture adaptation to reduce processor power consumption Ieee Micro. 25: 10-19. DOI: 10.1109/Mm.2005.70  0.323
2004 Zhang Z, Zhu Z, Zhang X. Design and optimization of large size and low overhead off-chip caches Ieee Transactions On Computers. 53: 843-855. DOI: 10.1109/Tc.2004.27  0.324
2001 Zhang Z, Zhu Z, Zhang X. Cached DRAM for ILP processor memory access latency reduction Ieee Micro. 21: 22-32. DOI: 10.1109/40.946676  0.324
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