| Year |
Citation |
Score |
| 2019 |
Le K, Ghaffari F, Kessal L, Declercq D, Boutillon E, Winstead C, Vasic B. A Probabilistic Parallel Bit-Flipping Decoder for Low-Density Parity-Check Codes Ieee Transactions On Circuits and Systems I: Regular Papers. 66: 403-416. DOI: 10.1109/Tcsi.2018.2849679 |
0.393 |
|
| 2015 |
Madsen C, Myers C, Roehner N, Winstead C, Zhang Z. Efficient analysis methods in synthetic biology. Methods in Molecular Biology (Clifton, N.J.). 1244: 217-57. PMID 25487100 DOI: 10.1007/978-1-4939-1878-2_11 |
0.345 |
|
| 2014 |
Madsen C, Zhang Z, Roehner N, Winstead C, Myers C. Stochastic model checking of genetic circuits Acm Journal On Emerging Technologies in Computing Systems. 11. DOI: 10.1145/2644817 |
0.35 |
|
| 2014 |
Sundararajan G, Winstead C, Boutillon E. Noisy gradient descent bit-flip decoding for LDPC codes Ieee Transactions On Communications. 62: 3385-3400. DOI: 10.1109/Tcomm.2014.2356458 |
0.32 |
|
| 2014 |
Winstead C, Boutillon E. Decoding LDPC codes with locally maximum-likelihood binary messages Ieee Communications Letters. 18: 2085-2088. DOI: 10.1109/Lcomm.2014.2366095 |
0.32 |
|
| 2012 |
Winstead C, Rodrigues JN. Ultra-low-power error correction circuits: Technology scaling and Sub-VT Operation Ieee Transactions On Circuits and Systems Ii: Express Briefs. 59: 913-917. DOI: 10.1109/Tcsii.2012.2231040 |
0.385 |
|
| 2012 |
Madsen C, Myers CJ, Patterson T, Roehner N, Stevens JT, Winstead C. Design and test of genetic circuits using iBioSim Ieee Design and Test of Computers. 29: 32-39. DOI: 10.1109/Mdt.2012.2187875 |
0.329 |
|
| 2010 |
Nguyen NP, Myers C, Kuwahara H, Winstead C, Keener J. Design and analysis of a robust genetic Muller C-element. Journal of Theoretical Biology. 264: 174-87. PMID 19914258 DOI: 10.1016/J.Jtbi.2009.10.026 |
0.353 |
|
| 2010 |
Sharifi Tehrani S, Winstead C, Gross WJ, Mannor S, Howard SL, Gaudet VC. Relaxation dynamics in stochastic iterative decoders Ieee Transactions On Signal Processing. 58: 5955-5961. DOI: 10.1109/Tsp.2010.2066269 |
0.346 |
|
| 2009 |
Winstead C, Howard S. A probabilistic LDPC-coded fault compensation technique for reliable nanoscale computing Ieee Transactions On Circuits and Systems Ii: Express Briefs. 56: 484-488. DOI: 10.1109/Tcsii.2009.2020946 |
0.368 |
|
| 2009 |
Jayaram M, Hamoui ME, Winstead C, Spencer E. Electronic design and modeling of an integrated plasma impedance probe Midwest Symposium On Circuits and Systems. 1139-1142. DOI: 10.1109/MWSCAS.2009.5235969 |
0.475 |
|
| 2009 |
Haley D, Gaudet V, Winstead C, Grant A, Schlegel C. A dual-function mixed-signal circuit for LDPC encoding/decoding Integration, the Vlsi Journal. 42: 332-339. DOI: 10.1016/J.Vlsi.2008.09.006 |
0.397 |
|
| 2008 |
Kashyap M, Winstead C. Decoding LDPC convolutional codes on Markov channels Eurasip Journal On Wireless Communications and Networking. 2008. DOI: 10.1155/2008/729180 |
0.33 |
|
| 2007 |
Yiu M, Winstead C, Gaudet V, Schlegel C. Design for testability of CMOS analog sum-product error-control decoders Ieee Transactions On Circuits and Systems Ii: Express Briefs. 54: 675-679. DOI: 10.1109/Tcsii.2007.898472 |
0.389 |
|
| 2006 |
Winstead C, Nguyen N, Gaudet VC, Schlegel C. Low-voltage CMOS circuits for analog iterative decoders Ieee Transactions On Circuits and Systems I: Regular Papers. 53: 829-841. DOI: 10.1109/Tcsi.2005.859773 |
0.386 |
|
| 2004 |
Winstead C, Dai J, Yu S, Myers C, Harrison RR, Schlegel C. CMOS analog MAP decoder for (8,4) Hamming code Ieee Journal of Solid-State Circuits. 39: 122-131. DOI: 10.1109/Jssc.2003.820845 |
0.393 |
|
| 2004 |
Nguyen N, Winstead C, Gaudet VC, Schlegel C. A 0.8V CMOS analog decoder for AN (8,4,4) extended hamming code Proceedings - Ieee International Symposium On Circuits and Systems. 1. |
0.302 |
|
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