☰

Yu-Min Lee, Ph.D. - Publications

Affiliations: 
2003 University of Wisconsin, Madison, Madison, WI 
Area:
Electronics and Electrical Engineering
Tree Info Similar researchers PubMed Report error

8 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2017 Lee Y, Ho C. InTraSim: Incremental Transient Simulation of Power Grids Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 36: 2052-2065. DOI: 10.1109/Tcad.2017.2681082  0.386
2016 Chiou H, Lee Y. Thermal Simulation for Two-Phase Liquid Cooling 3D-ICs Journal of Computational Chemistry. 4: 33-45. DOI: 10.4236/Jcc.2016.415003  0.34
2015 Lee YM, Pan CW, Huang PY, Yang CP. LUTSim: A Look-Up Table-Based Thermal Simulator for 3-D ICs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 34: 1250-1263. DOI: 10.1109/Tcad.2015.2401578  0.35
2009 Huang PY, Lee YM. Full-Chip thermal analysis for the early design stage via generalized integral transforms Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 17: 613-626. DOI: 10.1109/Tvlsi.2008.2006043  0.399
2005 Lee Y, Cao Y, Chen T, Wang JM, Chen CC-. HiPRIME: hierarchical and passivity preserved interconnect macromodeling engine for RLKC power delivery Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 797-806. DOI: 10.1109/Tcad.2005.847938  0.438
2003 Lee Y, Chen CC-. The power grid transient simulation in linear time based on 3-D alternating-direction-implicit method Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 22: 1545-1550. DOI: 10.1109/Tcad.2003.818373  0.445
2002 Lee YM, Chen CCP. Power grid transient simulation in linear time based on transmission-line-modeling alternating-direction-implicit method Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 21: 1343-1352. DOI: 10.1109/Tcad.2002.804082  0.463
2002 Lee Y, Chen CCP, Chang YW, Wong DF. Simultaneous Buffer-sizing and Wire-sizing for Clock Trees Based on Lagrangian Relaxation Vlsi Design. 15: 587-594. DOI: 10.1080/1065514021000012200  0.371
Show low-probability matches.