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Ricardo Augusto da Luz Reis - Publications

Affiliations: 
Universidade Federal do Rio Grande do Sul (UFRGS) 
Area:
Microelectronics, Physical Design, EDA, MPSoCs, Fault Tolerance
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31 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Brendler LH, Zimpeck AL, Meinhardt C, Reis R. Multi-Level Design Influences on Robustness Evaluation of 7nm FinFET Technology Ieee Transactions On Circuits and Systems I-Regular Papers. 67: 553-564. DOI: 10.1109/Tcsi.2019.2927374  0.379
2019 Rosa FRd, Garibotti R, Ost L, Reis R. Using Machine Learning Techniques to Evaluate Multicore Soft Error Reliability Ieee Transactions On Circuits and Systems I-Regular Papers. 66: 2151-2164. DOI: 10.1109/Tcsi.2019.2906155  0.362
2019 Ramos EdA, Bontorin G, Reis R. A New Nonlinear Global Placement for FPGAs: The Chaotic Place Ieee Transactions On Circuits and Systems I-Regular Papers. 66: 2165-2174. DOI: 10.1109/Tcsi.2019.2903215  0.317
2017 Rodrigues GS, Rosa F, Oliveira ABd, Kastensmidt FL, Ost L, Reis R. Analyzing the Impact of Fault-Tolerance Methods in ARM Processors Under Soft Errors Running Linux and Parallelization APIs Ieee Transactions On Nuclear Science. 64: 2196-2203. DOI: 10.1109/Tns.2017.2706519  0.367
2016 Chielle E, Rosa F, Rodrigues GS, Tambara LA, Tonfat J, Macchione E, Aguirre F, Added N, Medina N, Aguiar V, Silveira MAG, Ost L, Reis R, Cuenca-Asensi S, Kastensmidt FL. Reliability on ARM Processors Against Soft Errors Through SIHFT Techniques Ieee Transactions On Nuclear Science. 63: 2208-2216. DOI: 10.1109/Tns.2016.2525735  0.401
2016 Posser G, Mishra V, Jain P, Reis R, Sapatnekar SS. Cell-Internal Electromigration: Analysis and Pin Placement Based Optimization Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 220-231. DOI: 10.1109/Tcad.2015.2456427  0.365
2016 Bartra WEC, Vladimirescu A, Reis R. FDSOI and Bulk CMOS SRAM Cell Resilience to Radiation Effects Microelectronics Reliability. 64: 152-157. DOI: 10.1016/J.Microrel.2016.07.133  0.342
2016 Blokhina E, Deltimple N, Trocan M, Deval Y, Reis R, Barthélemy H. Introduction to the special issue on ICECS 2014 Analog Integrated Circuits and Signal Processing. 87: 101-103. DOI: 10.1007/S10470-016-0720-6  0.307
2015 Tonfat J, Kastensmidt FL, Rech P, Reis R, Quinn HM. Analyzing the effectiveness of a frame-level redundancy scrubbing technique for SRAM-based FPGAs Ieee Transactions On Nuclear Science. 62: 3080-3087. DOI: 10.1109/Tns.2015.2489601  0.377
2015 Rosa FR, Brum RM, Wirth G, Kastensmidt F, Ost L, Reis R. Impact of dynamic voltage scaling and thermal factors on SRAM reliability Microelectronics Reliability. 55: 1486-1490. DOI: 10.1016/J.Microrel.2015.07.013  0.316
2015 Ziesemer AM, Reis R. Physical design automation of transistor networks Microelectronic Engineering. 148: 122-128. DOI: 10.1016/J.Mee.2015.10.018  0.397
2014 Flach G, Reimann T, Posser G, Johann M, Reis R. Effective Method for Simultaneous Gate Sizing and $V$ th Assignment Using Lagrangian Relaxation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 33: 546-557. DOI: 10.1109/Tcad.2014.2305847  0.334
2014 Bartra WEC, Reis R. A set of Virtual Instruments to simulate radiation effects in CMOS circuits The Journal of Thoracic and Cardiovascular Surgery. 1643-1646. DOI: 10.1109/I2Mtc.2014.6861024  0.326
2014 Reimann T, Sze CCN, Reis R. Challenges of cell selection algorithms in industrial high performance microprocessor designs Integration, the Vlsi Journal. DOI: 10.1016/J.Vlsi.2015.09.001  0.344
2013 Guthaus MR, Wilke G, Reis R. Revisiting automated physical synthesis of high-performance clock networks Acm Transactions On Design Automation of Electronic Systems. 18. DOI: 10.1145/2442087.2442102  0.336
2012 Guthaus MR, Hu X, Wilke G, Flach G, Reis R. High-performance clock mesh optimization Acm Transactions On Design Automation of Electronic Systems. 17. DOI: 10.1145/2209291.2209306  0.338
2012 Posser G, Flach G, Wilke G, Reis R. Gate sizing using geometric programming Analog Integrated Circuits and Signal Processing. 73: 831-840. DOI: 10.1007/S10470-012-9943-3  0.335
2012 Kerhervé E, Reis R, Rozo AG. Special issue on IEEE LASCAS2010 Analog Integrated Circuits and Signal Processing. 70: 163-164. DOI: 10.1007/S10470-011-9824-1  0.388
2011 Violante M, Meinhardt C, Reis R, Reorda MS. A Low-Cost Solution for Deploying Processor Cores in Harsh Environments Ieee Transactions On Industrial Electronics. 58: 2617-2626. DOI: 10.1109/Tie.2011.2134054  0.337
2010 Sawicki S, Wilke G, Johann MO, Reis R. 3D-Via Driven Partitioning for 3D VLSI Integrated Circuits Clei Electronic Journal. 13. DOI: 10.19153/Cleiej.13.3.1  0.303
2010 Bastos RP, Sicard G, Kastensmidt F, Renaudin M, Reis R. Asynchronous circuits as alternative for mitigation of long-duration transient faults in deep-submicron technologies Microelectronics Reliability. 50: 1241-1246. DOI: 10.1016/J.Microrel.2010.07.014  0.372
2010 Brusamarello L, Neuberger G, Wirth GI, Da Silva R, Reis R, Murgai R, Reddy S, Walker W. Statistical analysis of hold time violations Journal of Computational Electronics. 9: 114-121. DOI: 10.1007/S10825-010-0322-Y  0.338
2009 Hentschke R, Narasimhan J, Johann M, Reis R. Maze routing steiner trees with delay versus wire length tradeoff Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 17: 1073-1086. DOI: 10.1109/Tvlsi.2009.2019798  0.316
2009 Bastos RP, Kastensmidt FL, Reis R. Design of a soft-error robust microprocessor Microelectronics Journal. 40: 1062-1068. DOI: 10.1016/J.Mejo.2008.10.001  0.373
2007 Indrusiak LS, Glesner M, Reis R. On the Evolution of Remote Laboratories for Prototyping Digital Electronic Systems Ieee Transactions On Industrial Electronics. 54: 3069-3077. DOI: 10.1109/Tie.2007.907010  0.335
2007 Han S, Chae S, Brisolara L, Carro L, Reis R, Guérin X, Jerraya AA. Memory-efficient multithreaded code generation from Simulink for heterogeneous MPSoC Design Automation For Embedded Systems. 11: 249-283. DOI: 10.1007/S10617-007-9009-4  0.319
2005 Neuberger G, Kastensmidt FGdL, Reis R. An automatic technique for optimizing Reed-Solomon codes to improve fault tolerance in memories Ieee Design & Test of Computers. 22: 50-58. DOI: 10.1109/Mdt.2005.2  0.326
2004 Kastensmidt FGdL, Neuberger G, Hentschke RF, Carro L, Reis R. Designing fault-tolerant techniques for SRAM-based FPGAs Ieee Design & Test of Computers. 21: 552-562. DOI: 10.1109/Mdt.2004.85  0.378
2003 Neuberger G, Lima Fd, Carro L, Reis R. A multiple bit upset tolerant SRAM memory Acm Transactions On Design Automation of Electronic Systems. 8: 577-590. DOI: 10.1145/944027.944038  0.367
2001 Cota É, Lima F, Rezgui S, Carro L, Velazco R, Lubaszewski M, Reis R. Synthesis of an 8051-Like Micro-Controller Tolerant to Transient Faults Journal of Electronic Testing. 17: 149-161. DOI: 10.1023/A:1011125927317  0.347
1999 Lima F, Johann M, Güntzel J, D'Avila E, Carro L, Reis R. Designing a Mask Programmable Matrix for Sequential Circuits Ieee Transactions On Very Large Scale Integration Systems. 439-446. DOI: 10.1007/978-0-387-35498-9_39  0.385
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