| Year |
Citation |
Score |
| 2020 |
Momose H, Kaneko T, Asai T. Systems and circuits for AI chips and their trends Japanese Journal of Applied Physics. 59: 050502. DOI: 10.35848/1347-4065/Ab839F |
0.31 |
|
| 2020 |
Hirayama Y, Asai T, Motomura M, Takamaeda S. A Hardware-efficient Weight Sampling Circuit for Bayesian Neural Networks International Journal of Networking and Computing. 10: 84-93. DOI: 10.15803/Ijnc.10.2_84 |
0.35 |
|
| 2019 |
Ando K, Ueyoshi K, Oba Y, Hirose K, Uematsu R, Kudo T, Ikebe M, Asai T, Takamaeda-Yamazaki S, Motomura M. Dither NN: Hardware/Algorithm Co-Design for Accurate Quantized Neural Networks Ieice Transactions On Information and Systems. 102: 2341-2353. DOI: 10.1587/Transinf.2019Pap0009 |
0.305 |
|
| 2018 |
Tanaka H, Akai-Kasaya M, TermehYousefi A, Hong L, Fu L, Tamukoh H, Tanaka D, Asai T, Ogawa T. A molecular neuromorphic network device consisting of single-walled carbon nanotubes complexed with polyoxometalate. Nature Communications. 9: 2693. PMID 30002369 DOI: 10.1038/S41467-018-04886-2 |
0.328 |
|
| 2018 |
Tanibata A, Schmid A, Takamaeda-Yamazaki S, Ikebe M, Motomura M, Asai T. Protocomputing Architecture over a Digital Medium Aiming at Real-Time Video Processing Complexity. 2018: 1-11. DOI: 10.1155/2018/3618621 |
0.334 |
|
| 2018 |
Ando K, Ueyoshi K, Orimo K, Yonekawa H, Sato S, Nakahara H, Takamaeda-Yamazaki S, Ikebe M, Asai T, Kuroda T, Motomura M. BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W Ieee Journal of Solid-State Circuits. 53: 983-994. DOI: 10.1109/Jssc.2017.2778702 |
0.333 |
|
| 2017 |
Ando K, Takamaeda-Yamazaki S, Ikebe M, Asai T, Motomura M. A Multithreaded CGRA for Convolutional Neural Network Processing Circuits and Systems. 8: 149-170. DOI: 10.4236/Cs.2017.86010 |
0.358 |
|
| 2017 |
Hida I, Takamaeda-Yamazaki S, Ikebe M, Motomura M, Asai T. A High Performance and Energy Efficient Microprocessor with a Novel Restricted Dynamically Reconfigurable Accelerator Circuits and Systems. 8: 134-147. DOI: 10.4236/Cs.2017.85009 |
0.343 |
|
| 2016 |
Ueyoshi K, Marukame T, Asai T, Motomura M, Schmid A. FPGA Implementation of a Scalable and Highly Parallel Architecture for Restricted Boltzmann Machines Circuits and Systems. 7: 2132-2141. DOI: 10.4236/Cs.2016.79185 |
0.325 |
|
| 2016 |
Nakada K, Miura K, Asai T. Dynamical systems design of silicon neurons using phase reduction method Nonlinear Theory and Its Applications, Ieice. 7: 95-109. DOI: 10.1587/Nolta.7.95 |
0.57 |
|
| 2016 |
Prati E, Giussani E, Ferrari G, Asai T. Noise-assisted transmission of spikes in Maeda–Makino artificial neuron arrays International Journal of Parallel, Emergent and Distributed Systems. 32: 278-286. DOI: 10.1080/17445760.2016.1189914 |
0.306 |
|
| 2016 |
Takano M, Asai T, Oya T. Design and evaluation of single-electron associative memory circuit International Journal of Parallel, Emergent and Distributed Systems. 32: 259-270. DOI: 10.1080/17445760.2016.1165219 |
0.429 |
|
| 2015 |
Ishimura K, Komuro K, Schmid A, Asai T, Motomura M. FPGA implementation of hardware-oriented reaction-diffusion cellular automata models Nonlinear Theory and Its Applications, Ieice. 6: 252-262. DOI: 10.1587/Nolta.6.252 |
0.305 |
|
| 2014 |
Lizeth G, Asai T, Motomura M. Application of nonlinear systems for designing low-power logic gates based on stochastic resonance Nonlinear Theory and Its Applications, Ieice. 5: 445-455. DOI: 10.1587/Nolta.5.445 |
0.328 |
|
| 2014 |
Lizeth GC, Asai T, Motomura M. Low-power asynchronous digital pipeline based on mismatch-tolerant logic gates Ieice Electronics Express. 11. DOI: 10.1587/Elex.11.20140632 |
0.411 |
|
| 2013 |
Nakada K, Miura K, Asai T. Dynamical system design for silicon neurons using phase reduction approach. Conference Proceedings : ... Annual International Conference of the Ieee Engineering in Medicine and Biology Society. Ieee Engineering in Medicine and Biology Society. Annual Conference. 2013: 4997-5000. PMID 24110857 DOI: 10.1109/EMBC.2013.6610670 |
0.606 |
|
| 2012 |
Nakada K, Asai T, Amemiya Y. An analog CMOS central pattern generator for interlimb coordination in quadruped locomotion. Ieee Transactions On Neural Networks. 14: 1356-65. PMID 18244582 DOI: 10.1109/Tnn.2003.816381 |
0.635 |
|
| 2012 |
Lizeth G, Asai T, Motomura M. Impact of Noise on Spike Transmission through Serially Connected Electrical FitzHugh-Nagumo Circuits with Subthreshold and Suprathreshold Interconductances Journal of Signal Processing. 16: 503-509. DOI: 10.2299/Jsp.16.503 |
0.338 |
|
| 2012 |
Utagawa A, Asai T, Amemiya Y. Noise-induced phase synchronization among analog mos oscillator circuits Fluctuation and Noise Letters. 11. DOI: 10.1142/S0219477512500071 |
0.392 |
|
| 2012 |
Nakada K, Miura K, Asai T, Tanaka HA. Dynamical systems design of nonlinear oscillators using phase reduction approach Ieee Asia-Pacific Conference On Circuits and Systems, Proceedings, Apccas. 308-311. DOI: 10.1109/APCCAS.2012.6419033 |
0.564 |
|
| 2011 |
Utagawa A, Asai T, Amemiya Y. Stochastic resonance in simple analog circuits with a single operational amplifier having a double-well potential Nonlinear Theory and Its Applications, Ieice. 2: 409-416. DOI: 10.1587/Nolta.2.409 |
0.408 |
|
| 2011 |
Utagawa A, Asai T, Amemiya Y. High-fidelity pulse density modulation in neuromorphic electric circuits utilizing natural heterogeneity Nonlinear Theory and Its Applications, Ieice. 2: 218-225. DOI: 10.1587/Nolta.2.218 |
0.428 |
|
| 2011 |
Fujita D, Asai T, Amemiya Y. A neuromorphic MOS circuit imitating jamming avoidance response of Eigenmannia Nonlinear Theory and Its Applications, Ieice. 2: 205-217. DOI: 10.1587/Nolta.2.205 |
0.422 |
|
| 2011 |
Oya T, Schmid A, Asai T, Utagawa A. Stochastic resonance in a balanced pair of single-electron boxes Fluctuation and Noise Letters. 10: 267-275. DOI: 10.1142/S0219477511000557 |
0.341 |
|
| 2011 |
Ueno K, Asai T, Amemiya Y. Low-power temperature-to-frequency converter consisting of subthreshold CMOS circuits for integrated smart temperature sensors Sensors and Actuators, a: Physical. 165: 132-137. DOI: 10.1016/J.Sna.2010.03.030 |
0.335 |
|
| 2010 |
Asai T, Ohtani M, Yonezu H. Analog integrated circuits for the Lotka-Volterra competitive neural networks. Ieee Transactions On Neural Networks. 10: 1222-31. PMID 18252623 DOI: 10.1109/72.788661 |
0.422 |
|
| 2010 |
Ueno K, Shimada H, Asai T, Amemiya Y. Low-voltage Power Supply Regulator for Subthreshold-operated CMOS Digital LSIs The Japan Society of Applied Physics. DOI: 10.7567/Ssdm.2010.G-4-4L |
0.317 |
|
| 2010 |
Tsugita Y, Ueno K, Hirose T, Asai T, Amemiya Y. An On-Chip PVT Compensation Technique with Current Monitoring Circuit for Low-Voltage CMOS Digital LSIs Ieice Transactions On Electronics. 93: 835-841. DOI: 10.1587/Transele.E93.C.835 |
0.428 |
|
| 2010 |
Asai S, Ueno K, Asai T, Amemiya Y. High-Resistance Resistor Consisting of a Subthreshold CMOS Differential Pair Ieice Transactions On Electronics. 93: 741-746. DOI: 10.1587/Transele.E93.C.741 |
0.364 |
|
| 2010 |
Akou N, Asai T, Yanagida T, Kawai T, Amemiya Y. A behavioral model of unipolar resistive RAMs and its application to HSPICE integration Ieice Electronics Express. 7: 1467-1473. DOI: 10.1587/Elex.7.1467 |
0.307 |
|
| 2010 |
Ueno K, Hirose T, Asai T, Amemiya Y. A 1-$\mu\hbox{W}$ 600- $\hbox{ppm}/^{\circ}\hbox{C}$ Current Reference Circuit Consisting of Subthreshold CMOS Circuits Ieee Transactions On Circuits and Systems Ii: Express Briefs. 57: 681-685. DOI: 10.1109/Tcsii.2010.2056051 |
0.396 |
|
| 2010 |
Gessyca T, Asai T, Amemiya Y. Neuromorphic CMOS analog circuit exhibiting array-enhanced stochastic resonance Behavior with population heterogeneity Neuroscience Research. 68: e213. DOI: 10.1016/J.Neures.2010.07.2514 |
0.357 |
|
| 2009 |
Kikombo AK, Asai T, Oya T, Schmid A, Leblebici Y. A Neuromorphic Single-Electron Circuit for Noise-Shaping Pulse-Density Modulation International Journal of Nanotechnology and Molecular Computation. 1: 80-92. DOI: 10.4018/Jnmc.2009040106 |
0.325 |
|
| 2009 |
Ueno K, Hirose T, Asai T, Amemiya Y. Floating millivolt reference for PTAT current generation in subthreshold MOS LSIs Kyokai Joho Imeji Zasshi/Journal of the Institute of Image Information and Television Engineers. 63: 1877-1880. DOI: 10.3169/Itej.63.1877 |
0.381 |
|
| 2009 |
Tsugita Y, Hirose T, Ueno K, Asai T, Amemiya Y. Process Compensation Techniques for Low-Voltage CMOS Digital Circuits The Journal of the Institute of Image Information and Television Engineers. 63: 1667-1670. DOI: 10.3169/Itej.63.1667 |
0.429 |
|
| 2009 |
Ogawa T, Hirose T, Asai T, Amemiya Y. Threshold-Logic Devices Consisting of Subthreshold CMOS Circuits Ieice Transactions On Fundamentals of Electronics, Communications and Computer Sciences. 92: 436-442. DOI: 10.1587/Transfun.E92.A.436 |
0.401 |
|
| 2009 |
Ueno K, Hirose T, Asai T, Amemiya Y. Low-Voltage Process-Compensated VCO with On-Chip Process Monitoring and Body-Biasing Circuit Techniques Ieice Transactions On Fundamentals of Electronics, Communications and Computer Sciences. 92: 3079-3081. DOI: 10.1587/Transfun.E92.A.3079 |
0.4 |
|
| 2009 |
Utagawa A, Sahashi T, Asai T, Amemiya Y. Stochastic Resonance in an Array of Locally-Coupled McCulloch-Pitts Neurons with Population Heterogeneity Ieice Transactions On Fundamentals of Electronics, Communications and Computer Sciences. 92: 2508-2513. DOI: 10.1587/Transfun.E92.A.2508 |
0.327 |
|
| 2009 |
Kikombo AK, Asai T, Amemiya Y. An elementary neuro-morphic circuit for visual motion detection with single-electron devices based on correlation neural networks Journal of Computational and Theoretical Nanoscience. 6: 89-95. DOI: 10.1166/Jctn.2009.1011 |
0.399 |
|
| 2009 |
Ueno K, Hirose T, Asai T, Amemiya Y. A 300 nW, 15 ppm/$^{\circ}$C, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs Ieee Journal of Solid-State Circuits. 44: 2047-2054. DOI: 10.1109/Jssc.2009.2021922 |
0.365 |
|
| 2009 |
Hirose T, Hagiwara A, Asai T, Amemiya Y. A highly sensitive thermosensing CMOS Circuit Based on self-biasing circuit technique Ieej Transactions On Electrical and Electronic Engineering. 4: 278-286. DOI: 10.1002/Tee.20404 |
0.393 |
|
| 2008 |
Ueno K, Asai T, Amemiya Y. Current Reference Circuit for Subthreshold CMOS LSIs The Japan Society of Applied Physics. DOI: 10.7567/Ssdm.2008.F-7-1 |
0.401 |
|
| 2008 |
Hirose T, Asai T, Amemiya Y. Temperature-compensated CMOS current reference circuit for ultralow-power subthreshold LSIs Ieice Electronics Express. 5: 204-210. DOI: 10.1587/Elex.5.204 |
0.387 |
|
| 2008 |
Kasai S, Asai T. Stochastic Resonance in Schottky Wrap Gate-controlled GaAs Nanowire Field-Effect Transistors and Their Networks Applied Physics Express. 1: 083001. DOI: 10.1143/Apex.1.083001 |
0.372 |
|
| 2008 |
Nakada K, Igarashi J, Asai T, Tateno K, Hayashi H, Ohtubo Y, Miki T, Yoshii K. Stochastic synchronization and array-enhanced coherence resonance in a bio-inspired chemical sensor array Proceedings - 2008 Ieee 11th International Conference On Computational Science and Engineering, Cse 2008. 307-312. DOI: 10.1109/CSE.2008.45 |
0.513 |
|
| 2008 |
Utagawa A, Asai T, Hirose T, Amemiya Y. Noise-Induced Synchronization among Sub-RF CMOS Analog Oscillators for Skew-Free Clock Distribution Ieice Transactions On Fundamentals of Electronics, Communications and Computer Sciences. 91: 2475-2481. DOI: 10.1093/Ietfec/E91-A.9.2475 |
0.392 |
|
| 2008 |
Asai T, Yamada K, Amemiya Y. Single-flux-quantum logic circuits exploiting collision-based fusion gates Physica C: Superconductivity. 468: 1983-1986. DOI: 10.1016/J.Physc.2008.05.273 |
0.388 |
|
| 2008 |
Kikombo AK, Hirose T, Asai T, Amemiya Y. Non-linear phenomena in electronic systems consisting of coupled single-electron oscillators Chaos, Solitons & Fractals. 37: 100-107. DOI: 10.1016/J.Chaos.2007.08.036 |
0.305 |
|
| 2007 |
Ueno K, Hirose T, Asai T, Amemiya Y. CMOS Voltage Reference Based on the Threshold Voltage of a MOSFET The Japan Society of Applied Physics. 2007: 486-487. DOI: 10.7567/Ssdm.2007.P-5-4 |
0.334 |
|
| 2007 |
Oya T, Motoike IN, Asai T. Single-electron circuits performing dendritic pattern formation with nature-inspired cellular automata International Journal of Bifurcation and Chaos. 17: 3651-3655. DOI: 10.1142/S0218127407019512 |
0.396 |
|
| 2007 |
KIKOMBO AK, OYA T, ASAI T, AMEMIYA Y. DISCRETE DYNAMICAL SYSTEMS CONSISTING OF SINGLE-ELECTRON CIRCUITS International Journal of Bifurcation and Chaos. 17: 3613-3617. DOI: 10.1142/S0218127407019457 |
0.387 |
|
| 2007 |
TAKAHASHI M, ASAI T, HIROSE T, AMEMIYA Y. A CMOS REACTION–DIFFUSION DEVICE USING MINORITY-CARRIER DIFFUSION IN SEMICONDUCTORS International Journal of Bifurcation and Chaos. 17: 1713-1719. DOI: 10.1142/S0218127407018014 |
0.351 |
|
| 2007 |
Utagawa A, Asai T, Hirose T, Amemiya Y. An Inhibitory Neural-Network Circuit Exhibiting Noise Shaping with Subthreshold MOS Neuron Circuits Ieice Transactions On Fundamentals of Electronics, Communications and Computer Sciences. 90: 2108-2115. DOI: 10.1093/Ietfec/E90-A.10.2108 |
0.424 |
|
| 2007 |
Hirose T, Asai T, Amemiya Y. Pulsed Neural Networks Consisting of Single-Flux-Quantum Spiking Neurons Physica C-Superconductivity and Its Applications. 463: 1072-1075. DOI: 10.1016/J.Physc.2007.02.043 |
0.36 |
|
| 2007 |
Nakada K, Asai T, Hirose T, Hayashi H, Amemiya Y. A subthreshold CMOS circuit for a piecewise linear neuromorphic oscillator with current-mode low-pass filters Neurocomputing. 71: 3-12. DOI: 10.1016/J.Neucom.2006.11.026 |
0.644 |
|
| 2007 |
Nakada K, Asai T, Hayashi H. Synchronization properties of pulse-coupled resonate-and-fire neuron circuits and their application International Congress Series. 1301: 148-151. DOI: 10.1016/J.ICS.2006.12.020 |
0.567 |
|
| 2007 |
Oya T, Asai T, Amemiya Y. Stochastic resonance in an ensemble of single-electron neuromorphic devices and its application to competitive neural networks Chaos, Solitons and Fractals. 32: 855-861. DOI: 10.1016/J.Chaos.2005.11.027 |
0.387 |
|
| 2006 |
Nakada K, Asai T, Hayashi H. Analog VLSI implementation of resonate-and-fire neuron. International Journal of Neural Systems. 16: 445-56. PMID 17285690 DOI: 10.1142/S0129065706000846 |
0.659 |
|
| 2006 |
Hirose T, Asai T, Amemiya Y. Power-supply circuits for ultralow-power subthreshold MOS-LSIs Ieice Electronics Express. 3: 464-468. DOI: 10.1587/Elex.3.464 |
0.358 |
|
| 2006 |
Yamada K, Motoike IN, Asai T, Amemiya Y. Design methodologies for compact logic circuits based on collision-based computing Ieice Electronics Express. 3: 292-298. DOI: 10.1587/Elex.3.292 |
0.404 |
|
| 2006 |
ASAI T, KAMIYA T, HIROSE T, AMEMIYA Y. A SUBTHRESHOLD ANALOG MOS CIRCUIT FOR LOTKA–VOLTERRA CHAOTIC OSCILLATOR International Journal of Bifurcation and Chaos. 16: 207-212. DOI: 10.1142/S0218127406014733 |
0.369 |
|
| 2006 |
Hirose T, Asai T, Amemiya Y. Spiking neuron devices consisting of single-flux-quantum circuits Physica C-Superconductivity and Its Applications. 445: 1020-1023. DOI: 10.1016/J.Physc.2006.05.093 |
0.353 |
|
| 2006 |
Oya T, Asai T, Kagaya R, Hirose T, Amemiya Y. Neuronal synchrony detection on single-electron neural networks Chaos, Solitons and Fractals. 27: 887-894. DOI: 10.1016/J.Chaos.2005.04.059 |
0.344 |
|
| 2006 |
Suzuki Y, Takayama T, Motoike IN, Asai T. A reaction-diffusion model performing stripe- and spot-image restoration and its LSI implementation Electronics and Communications in Japan (Part Iii: Fundamental Electronic Science). 90: 20-29. DOI: 10.1002/Ecjc.20243 |
0.316 |
|
| 2005 |
Kagaya R, Ikebe M, Asai T, Amemiya Y. On-Chip Fixed-Pattern-Noise Canceling by Negative-Feedback Reset for CMOS Image Sensors The Journal of the Institute of Image Information and Television Engineers. 59: 415-421. DOI: 10.3169/Itej.59.415 |
0.325 |
|
| 2005 |
Ikebe M, Asai T. A Digital Vision Chip for Early Feature Extraction with Rotated Template-Matching CA Journal of Robotics and Mechatronics. 17: 372-377. DOI: 10.20965/Jrm.2005.P0372 |
0.334 |
|
| 2005 |
ASAI T, COSTELLO BDL, ADAMATZKY A. SILICON IMPLEMENTATION OF A CHEMICAL REACTION–DIFFUSION PROCESSOR FOR COMPUTATION OF VORONOI DIAGRAM International Journal of Bifurcation and Chaos. 15: 3307-3320. DOI: 10.1142/S0218127405013903 |
0.317 |
|
| 2005 |
Nakada K, Asai T, Amemiya Y. Analog CMOS implementation of a CNN-based locomotion controller with floating-gate devices Ieee Transactions On Circuits and Systems I: Regular Papers. 52: 1095-1103. DOI: 10.1109/Tcsi.2005.849120 |
0.667 |
|
| 2005 |
Hirose T, Matsuoka T, Taniguchi K, Asai T, Amemiya Y. Ultralow-Power Current Reference Circuit with Low Temperature Dependence Ieice Transactions On Electronics. 88: 1142-1147. DOI: 10.1093/Ietele/E88-C.6.1142 |
0.342 |
|
| 2005 |
Asai T, Ikebe M, Hirose T, Amemiya Y. A quadrilateral-object composer for binary images with reaction–diffusion cellular automata International Journal of Parallel, Emergent and Distributed Systems. 20: 57-67. DOI: 10.1080/17445760500033390 |
0.316 |
|
| 2004 |
Nakada K, Asai T, Amemiya Y. Biologically-Inspired Locomotion Controller for a Quadruped Walking Robot: Analog IC Implementation of a CPG-Based Controller Journal of Robotics and Mechatronics. 16: 397-403. DOI: 10.20965/Jrm.2004.P0397 |
0.546 |
|
| 2004 |
Kanazawa Y, Asai T, Hirose T, Amemiya Y. A MOS circuit for bursting neural oscillators with excitable oregonators Ieice Electronics Express. 1: 73-76. DOI: 10.1587/Elex.1.73 |
0.457 |
|
| 2004 |
Matsubara H, Asai T, Hirose T, Amemiya Y. Reaction-diffusion chip implementing excitable lattices with multiple-valued cellular automata Ieice Electronics Express. 1: 248-252. DOI: 10.1587/Elex.1.248 |
0.365 |
|
| 2004 |
Nakada K, Asai T, Amemiya Y. Design of an Artificial Central Pattern Generator with Feedback Controller Intelligent Automation & Soft Computing. 10: 185-192. DOI: 10.1080/10798587.2004.10642876 |
0.576 |
|
| 2003 |
Kanazawa Y, Asai T, Amemiya Y. Basic Circuit Design of a Neural Processor: Analog CMOS Implementation of Spiking Neurons and Dynamic Synapses Journal of Robotics and Mechatronics. 15: 208-218. DOI: 10.20965/Jrm.2003.P0208 |
0.42 |
|
| 2003 |
Asai T, Kanazawa Y, Amemiya Y. A Subthreshold MOS Neuron Circuit Based on the Volterra System Ieee Transactions On Neural Networks. 14: 1308-1312. DOI: 10.1109/Tnn.2003.816357 |
0.436 |
|
| 2003 |
Oya T, Asai T, Fukui T, Amemiya Y. A majority-logic device using an irreversible single-electron box Ieee Transactions On Nanotechnology. 2: 15-22. DOI: 10.1109/Tnano.2003.808507 |
0.398 |
|
| 2003 |
Oya T, Asai T, Amemiya Y. Single-electron logic device with simple structure Electronics Letters. 39: 965-967. DOI: 10.1049/El:20030613 |
0.362 |
|
| 2003 |
Oya T, Takahashi Y, Ikebe M, Asai T, Amemiya Y. A single-electron circuit as a discrete dynamical system Superlattices and Microstructures. 34: 253-258. DOI: 10.1016/J.Spmi.2004.03.016 |
0.389 |
|
| 2002 |
Oya T, Asai T, Fukui T, Amemiya Y. A majority-logic nanodevice using a balanced pair of single-electron boxes. Journal of Nanoscience and Nanotechnology. 2: 333-42. PMID 12908260 DOI: 10.1166/Jnn.2002.108 |
0.4 |
|
| 2002 |
Yamada T, Honma Y, Asai T, Amemiya Y. Reaction-diffusion chip implementing analog cellular-automaton model The Japan Society of Applied Physics. DOI: 10.7567/Ssdm.2002.P1-1 |
0.373 |
|
| 2001 |
Asai T, Sunayama T, Amemiya Y, Ikebe M. A νMOS Vision Chip Based on Cellular-Automaton Processing Japanese Journal of Applied Physics. 40: 2585-2592. DOI: 10.1143/Jjap.40.2585 |
0.331 |
|
| 2001 |
Yamada T, Akazawa M, Asai T, Amemiya Y. Boltzmann machine neural network devices using single-electron tunnelling Nanotechnology. 12: 60-67. DOI: 10.1088/0957-4484/12/1/311 |
0.404 |
|
| 2001 |
Inokuchi T, Yamada T, Asai T, Amemiya Y. Analog computation using quantum-flux parametron devices Physica C: Superconductivity and Its Applications. 357: 1618-1621. DOI: 10.1016/S0921-4534(01)00569-X |
0.301 |
|
| 2000 |
Sunayama T, Ikebe M, Asai T, Amemiya Y. Cellular νMOS Circuits Performing Edge Detection with Difference-of-Gaussian Filters Japanese Journal of Applied Physics. 39: 2278-2286. DOI: 10.1143/Jjap.39.2278 |
0.431 |
|
| 2000 |
Ohtani M, Yonezu H, Asai T. Analog Metal-Oxide-Silicon IC Implementation of Motion-Detection Network Based on a Biological Correlation Model Japanese Journal of Applied Physics. 39: 1160-1164. DOI: 10.1143/Jjap.39.1160 |
0.319 |
|
| 1999 |
Asai T, Fukai T, Tanaka S. A subthreshold MOS circuit for the Lotka-Volterra neural network producing the winners-share-all solution. Neural Networks : the Official Journal of the International Neural Network Society. 12: 211-216. PMID 12662698 DOI: 10.1016/S0893-6080(98)00121-X |
0.59 |
|
| 1999 |
Asai T, Ohtani M, Yonezu H. Analog MOS Circuits for Motion Detection Based on Correlation Neural Networks Japanese Journal of Applied Physics. 38: 2256-2261. DOI: 10.1143/Jjap.38.2256 |
0.389 |
|
| 1998 |
Ohtani M, Asai T, Ohshima N, Yonezu H. An Analog Integrated Circuit for Motion Detection Based on Biological Correlation Model The Japan Society of Applied Physics. 1998: 82-83. DOI: 10.7567/Ssdm.1998.D-1-4 |
0.326 |
|
| 1998 |
Ikeda H, Tsuji K, Asai T, Yonezu H, Shin JK. A novel retina chip with simple wiring for edge extraction Ieee Photonics Technology Letters. 10: 261-263. DOI: 10.1109/68.655378 |
0.339 |
|
| 1997 |
Ikeda H, Tsuji K, Asai T, Yonezu H, Shin J. An Adaptive Silicon Retina Performing an Edge Extraction with a MOS-Type Spatial Wiring and Smart Pixel Circuits The Japan Society of Applied Physics. 1997: 386-387. DOI: 10.7567/Ssdm.1997.C-10-6 |
0.317 |
|
| 1996 |
Asai T, Yokotsuka H, Fukai T. A MOS circuit for a nonmonotonic neural network with excellent retrieval capabilities. Ieee Transactions On Neural Networks / a Publication of the Ieee Neural Networks Council. 7: 182-9. PMID 18255568 DOI: 10.1109/72.478402 |
0.559 |
|
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