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Dae Hyun Kim - Publications

Affiliations: 
2012 Georgia Institute of Technology, Atlanta, GA 
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19 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Musavvir S, Chatterjee A, Kim RG, Kim DH, Pande PP. Inter-Tier Process-Variation-Aware Monolithic 3-D NoC Design Space Exploration Ieee Transactions On Very Large Scale Integration Systems. 28: 686-699. DOI: 10.1109/Tvlsi.2019.2954770  0.362
2020 Chaudhuri A, Banerjee S, Park H, Kim J, Murali G, Lee E, Kim D, Lim SK, Mukhopadhyay S, Chakrabarty K. Advances in Design and Test of Monolithic 3-D ICs Ieee Design & Test of Computers. 37: 92-100. DOI: 10.1109/Mdat.2020.2988657  0.431
2019 Kim D, Hsu S, Milor L. Optimization of Experimental Designs for System- Level Accelerated Life Test in a Memory System Degraded by Time-Dependent Dielectric Breakdown Ieee Transactions On Very Large Scale Integration Systems. 27: 1640-1651. DOI: 10.1109/Tvlsi.2019.2909086  0.384
2019 Lin SD, Kim DH. Wire Length Characteristics of Multi-Tier Gate-Level Monolithic 3D ICs Ieee Transactions On Emerging Topics in Computing. 7: 301-310. DOI: 10.1109/Tetc.2016.2630064  0.473
2019 Long Y, Kim D, Lee E, Saha P, Mudassar BA, She X, Khan AI, Mukhopadhyay S. A Ferroelectric FET-Based Processing-in-Memory Architecture for DNN Acceleration Ieee Journal On Exploratory Solid-State Computational Devices and Circuits. 5: 113-122. DOI: 10.1109/Jxcdc.2019.2923745  0.438
2018 Lee D, Das S, Kim DH, Doppa JR, Pande PP. Design Space Exploration of 3D Network-on-Chip Acm Journal On Emerging Technologies in Computing Systems. 14: 1-26. DOI: 10.1145/3197567  0.375
2018 Hong I, Kim DH. Analysis of Performance Benefits of Multitier Gate-Level Monolithic 3-D Integrated Circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 1614-1626. DOI: 10.1109/Tcad.2017.2768427  0.452
2018 Lin SD, Kim DH. Detailed-Placement-Enabled Dynamic Power Optimization of Multitier Gate-Level Monolithic 3-D ICs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 845-854. DOI: 10.1109/Tcad.2017.2729401  0.41
2017 Kim D, Milor L. An ECC-Assisted Postpackage Repair Methodology in Main Memory Systems Ieee Transactions On Very Large Scale Integration Systems. 25: 2045-2058. DOI: 10.1109/Tvlsi.2017.2671790  0.321
2016 Kim DH, Lim SK. Guest Editors' Introduction: Advances in 3-D Integrated Circuits, Systems, and CAD Tools-Part 2 Ieee Design and Test. 33: 7-8. DOI: 10.1109/Mdat.2016.2519718  0.454
2015 Kim DH, Athikulwongse K, Healy MB, Hossain MM, Jung M, Khorosh I, Kumar G, Lee YJ, Lewis DL, Lin TW, Liu C, Panth S, Pathak M, Ren M, Shen G, et al. Design and analysis of 3D-MAPS (3D Massively parallel processor with stacked memory) Ieee Transactions On Computers. 64: 112-125. DOI: 10.1109/Tc.2013.192  0.494
2015 Kim DH, Lim SK. Physical Design and CAD Tools for 3-D Integrated Circuits: Challenges and Opportunities Ieee Design & Test of Computers. 32: 8-22. DOI: 10.1109/Mdat.2015.2440317  0.424
2015 Kim DH, Nair PJ, Qureshi MK. Architectural support for mitigating row hammering in DRAM memories Ieee Computer Architecture Letters. 14: 9-12. DOI: 10.1109/Lca.2014.2332177  0.383
2014 Kim DH, Mukhopadhyay S, Lim SK. TSV-Aware Interconnect Distribution Models for Prediction of Delay and Power Consumption of 3-D Stacked ICs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 33: 1384-1395. DOI: 10.1109/Tcad.2014.2329472  0.372
2013 Kim DH, Athikulwongse K, Lim SK. Study of Through-Silicon-Via Impact on the 3-D Stacked IC Layout Ieee Transactions On Very Large Scale Integration Systems. 21: 862-874. DOI: 10.1109/Tvlsi.2012.2201760  0.69
2012 Kim DH, Lim SK. Design Quality Trade-Off Studies for 3-D ICs Built With Sub-Micron TSVs and Future Devices Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 2: 240-248. DOI: 10.1109/Jetcas.2012.2193840  0.448
2011 Cho M, Liu C, Kim DH, Lim SK, Mukhopadhyay S. Pre-Bond and Post-Bond Test and Signal Recovery Structure to Characterize and Repair TSV Defect Induced Signal Degradation in 3-D System Ieee Transactions On Components, Packaging and Manufacturing Technology. 1: 1718-1727. DOI: 10.1109/Tcpmt.2011.2166961  0.351
2011 Kim DH, Mukhopadhyay S, Lim SK. Fast and Accurate Analytical Modeling of Through-Silicon-Via Capacitive Coupling Ieee Transactions On Components, Packaging and Manufacturing Technology. 1: 168-180. DOI: 10.1109/Tcpmt.2010.2101910  0.309
2008 Bae S, Park K, Ihm J, Song H, Lee W, Kim H, Kim K, Park Y, Park M, Lee H, Bang S, Moon G, Hwang S, Cho Y, Hwang S, ... Kim D, et al. An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion Ieee Journal of Solid-State Circuits. 43: 121-131. DOI: 10.1109/Jssc.2007.908002  0.305
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