Year |
Citation |
Score |
2017 |
Jung M, Song T, Peng Y, Lim SK. Design Methodologies for Low-Power 3-D ICs With Advanced Tier Partitioning Ieee Transactions On Very Large Scale Integration Systems. 25: 2109-2117. DOI: 10.1109/Tvlsi.2017.2670508 |
0.776 |
|
2017 |
Peng Y, Song T, Petranovic D, Lim SK. Parasitic Extraction for Heterogeneous Face-to-Face Bonded 3-D ICs Ieee Transactions On Components, Packaging and Manufacturing Technology. 7: 912-924. DOI: 10.1109/Tcpmt.2017.2677963 |
0.755 |
|
2015 |
Song T, Lim SK. Full-Chip Power/Performance Benefits of Carbon Nanotube-Based Circuits Journal of Information and Communication Convergence Engineering. 13: 180-188. DOI: 10.6109/Jicce.2015.13.3.180 |
0.394 |
|
2015 |
Song T, Lim SK. Die-to-Die Parasitic Extraction Targeting Face-to-Face Bonded 3D ICs Journal of Information and Communication Convergence Engineering. 13: 172-179. DOI: 10.6109/Jicce.2015.13.3.172 |
0.461 |
|
2015 |
Song T, Liu C, Peng Y, Lim SK. Full-Chip Signal Integrity Analysis and Optimization of 3-D ICs Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. DOI: 10.1109/Tvlsi.2015.2471098 |
0.751 |
|
2015 |
Jung M, Song T, Peng Y, Lim SK. Fine-Grained 3-D IC Partitioning Study With a Multicore Processor Ieee Transactions On Components, Packaging and Manufacturing Technology. DOI: 10.1109/Tcpmt.2015.2470124 |
0.725 |
|
2015 |
Kim DH, Athikulwongse K, Healy MB, Hossain MM, Jung M, Khorosh I, Kumar G, Lee YJ, Lewis DL, Lin TW, Liu C, Panth S, Pathak M, Ren M, Shen G, ... Song T, et al. Design and analysis of 3D-MAPS (3D Massively parallel processor with stacked memory) Ieee Transactions On Computers. 64: 112-125. DOI: 10.1109/Tc.2013.192 |
0.543 |
|
2014 |
Peng Y, Song T, Petranovic D, Lim SK. Silicon Effect-Aware Full-Chip Extraction and Mitigation of TSV-to-TSV Coupling Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 33: 1900-1913. DOI: 10.1109/Tcad.2014.2359578 |
0.748 |
|
2011 |
Cho J, Song E, Yoon K, Pak JS, Kim J, Lee W, Song T, Kim K, Lee J, Lee H, Park K, Yang S, Suh M, Byun K, Kim J. Modeling and Analysis of Through-Silicon Via (TSV) Noise Coupling and Suppression Using a Guard Ring Ieee Transactions On Components, Packaging and Manufacturing Technology. 1: 220-233. DOI: 10.1109/Tcpmt.2010.2101892 |
0.473 |
|
2011 |
Kim J, Pak JS, Cho J, Song E, Kim H, Song T, Lee J, Lee H, Park K, Yang S, Suh MS, Byun KY. High-frequency scalable electrical model and analysis of a through silicon via (TSV) Ieee Transactions On Components, Packaging and Manufacturing Technology. 1: 181-195. DOI: 10.1109/Tcpmt.2010.2101890 |
0.374 |
|
2011 |
Pak JS, Kim J, Cho J, Kim K, Song T, Ahn S, Lee J, Lee H, Park K, Kim J. PDN Impedance Modeling and Analysis of 3D TSV IC by Using Proposed P/G TSV Array Model Based on Separated P/G TSV and Chip-PDN Models Ieee Transactions On Components, Packaging and Manufacturing Technology. 1: 208-219. DOI: 10.1109/Tcpmt.2010.2101771 |
0.462 |
|
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