Vladimir Stojanovic, Ph.D. - US grants

Integrative, Hybrid and Complex Systems
Vladimir M. Stojanovic, Massachusetts Institute of Technology
Aleksandar Kavcic, University of Hawaii
Collaborative Research: Energy-efficient Communication with Optimized ECC Decoders: Connecting Algorithms and Implementations


Intellectual Merit: In a classical unidirectional communication system, the transmitter and the receiver functions are optimized separately. Recently, bidirectional, power-constrained communication systems have emerged, such as for wireless mobile devices and high-speed interconnections within digital systems, where both the transmitter and the receiver draw power from the same supply and where their joint power consumption affects the data rate and the energy-efficiency of the whole system. Thus, the transmitter and the receiver need to be jointly optimized. This research pursues a strategy to jointly optimize severely power-constrained communication systems to achieve a balance between speed (data rate), performance (in terms of error rate), and power consumption. The strategy uses special families of decoders of error correction codes (ECCs) that allow tradeoffs in complexity and power consumption for performance. The research considers the entire engineering design, from theoretical inception to very large-scale integration (VLSI) implementation, including the feedback loop from the VLSI design layer to the algorithm development layer.

Broader Impact: This research has the potential to reduce power consumption in wireless mobile communication, where battery life is critical, through an integrative approach. Results of this research will be incorporated into a communication system design course at MIT. Course material will be made freely available through MIT's OpenCourseWare (OCW) website. Similar course improvements are planned at the University of Hawaii.

This award is funded under the American Recovery and Reinvestment Act of 2009 (Public Law 111-5).

The objective of this research is to overcome the limited bandwidth density and energy scaling of electrical interconnects, which have caused a slow-down in performance scaling of advanced integrated systems like manycore processors. The approach is to create scalable and robust transceiver circuits with integrated monolithic silicon photonics to provide seamless optical on-chip and off-chip communication with extremely high energy-efficiency and bandwidth density.

Intellectual merit: This research transforms the traditional research and design approaches by developing novel communication and circuit techniques through tight interaction with photonic device properties. Proposed solutions include robust, highly-digital circuits and system techniques for energy efficient nonlinear equalization and modulation as well as high-sensitivity optical data and clock receivers, and circuits for temperature control, testing and characterization.

Broader impacts: This research will enable continued performance scaling of data centers and internet routers, and bring significant benefits to the national economy by preserving the massive investments and introducing the photonic technology into advanced CMOS foundries. Through MIT programs like Interphase Pre-UROP, Women Technology Program, and K-12 Educational Outreach Summer Program the project will engage women and minority undergraduate and high-school students and teachers in multi-disciplinary aspects of experimental research and design in engineering. A newly developed graduate course in communication circuit and system design will be adapted for senior-level undergraduates and co-development of entry-level undergraduate class. These courses, design tools and projects will be available on the internet through MIT Open Course Ware initiative.

The objective of this research is to develop low-power, robust, and energy-efficient sensors to satisfy a wide range of current applications including large-scale networks and implantable biomedical sensors. The aim is to develop the fundamental framework for sensor systems, connecting theory and algorithms with efficient hardware implementations and circuit metrics, such as power, footprint, quantization effects, and other circuit and channel non-idealities. The approach is to develop compressed sensing techniques that result in universal and efficient sensor designs.

Intellectual Merit: The transformative aspect of this research is a joint investigation into both theoretical and hardware development of compressed sensing techniques for sensor systems. The plan is to optimize energy allocation in the information chain, by shifting from (the original) randomization techniques to more energy-efficient deterministic sensing techniques. The focus is on regimes relevant to practice, and the results of this research are foreseen to greatly impact both systems and hardware communities.

Broader Impacts: Energy-efficient sensor nodes are in great demand today. For example in large-scale networks and implantable sensors, low power nodes are required to increase the average node life-time until maintenance, as well as improve the patient's quality of life. The goal is to convince practitioners, that compressed sensing can be mapped to hardware-efficient implementations. By creating an online portal, the project will also demonstrate the benefits of the developed sensing techniques to both experts and general population. To disseminate the fundamental systems/hardware framework, a new multi-disciplinary course will be created at MIT and offered to a wide-range of students.

Fifth-generation (5G) wireless systems are expected to provide enormous improvements in data rates available to users, as well as much improvement overall user experience. Massive multiple-input multiple-output (MIMO) arrays consist of hundreds of antenna elements, serving many users and are considered to be a cornerstone of 5G wireless systems, and are expected to dramatically improve both the radio spectrum utilization and user experience. At the same time, the use of millimeter-wave (mm-wave) frequencies is supposed to provide additional spectrum for new services in the years to come, and small physical antenna separation makes mm-wave attractive for massive MIMO. While there has been substantial progress in the development of the theoretical concepts associated with the design of massive MIMO systems, very little work has been done to actually design a mm-wave massive MIMO system and on the network techniques needed to scale these systems to dozens of simultaneous spatial streams. This proposal addresses the key challenges in the development of signal processing algorithms, network protocols, and a prototype hardware design to enable scalable low-latency mm-wave MIMO networks with high degrees of spatial multiplexing. It will provide a path to a hundred-fold improvement in user data rates.

By integrating the theoretical system aspects with its practical development, this proposal addresses critical challenges for the development of mm-wave massive MIMO technologies. In particular, this project aims to achieve: (1) a mm-wave massive MIMO array architecture suitable for low-cost and energy-efficient deployment at massive scale, (2) an optimized scalable signal processing approach to massive MIMO array processing, which includes hybrid beamforming, distributed channel estimation and distributed beamforming, (3) a medium-access control (MAC) technique suitable for low-latency, low-coherence time applications by leveraging a full-duplex frame to enable rapid user acquisition, synchronization, tracking, and paging, (4) practical in-band full-duplex operation, realized through a combination of antenna array design, spatial filtering, and adaptive analog and digital cancellation, (5) practical front-end circuits with linearity and phase noise suitable for a large number of simultaneous spatial streams, and (6) a mm-wave massive MIMO test bed designed in a modular manner to enable future development and performance measurements of signal processing and MAC techniques. In addition to cross-disciplinary training of students involved in this project, interaction of project members with industry leaders will dramatically accelerate the penetration of 5G wireless communications.

Our society is on the cusp of a new revolution in integrated circuit technology and manufacturing. The new technology will successfully combine electronic and photonic systems creating previously unimagined functionality and performance. Such sophisticated electronic-photonic systems-on-chip with highly-efficient use of area, energy and spectral resources are critically needed in many communication scenarios. For example, current data-centers and high-performance supercomputers are both power-constrained. High-bandwidth density and high-energy efficiency photonic interconnects would allow the connectivity down to the processor chip level increasing the power-efficiency and utilization of the whole data-center, significantly impacting the national energy consumption in the next decade. However, the lack of large-scale integration approach, design methodology and unified cross-layer design has prevented the realization of these systems. The impact of the electronic-photonic designs and system design methodology proposed in this project spans not only communication systems, but also a variety of other sophisticated electronic-photonic systems (e.g. detection, sensing, and instrumentation). The multi-disciplinary work will educate a unique crop of engineers and scientists that cross the boundaries of electronic and photonic systems.

The objective of the research project is to utilize recently developed large-scale electronic-photonic integration approaches to design short-reach coherent-modulation photonic links that significantly improve the area, energy and spectral-efficiency. The proposed electronic-photonic circuit topologies for coherent high-order modulation transmitters and receivers leverage the advantages of each domain and correct for the non-idealities in the other. Starting from the modeling and simulation infrastructure, the proposed research comprises a unique simulation and modeling framework in Verilog-A, which allows for true co-simulation of photonic and electronic circuits, under large signal, non-linear, time-varying conditions. This capability gives vital insights into the interaction of electronic and photonic circuits. It is essential for the use of the resonant components as the second key ingredient in designing efficient electronic-photonic communication systems. Although energy and area efficient, the resonant components require sophisticated wavelength stabilization loops and electronic drive to compensate for their transfer-function characteristics, which are enabled by the co-simulation methodology and abundance of high-performance transistors in the proposed integration approaches.

The amount of new data generated by humanity in the past year exceeds that created in all of human history before. The processing demands of this data are driving the continued need for greater computational power, in domains including big data analytics, artificial intelligence, and augmented reality, serving technologies including personal, medical, research, engineering, finance, and weather prediction. As "Moore's Law" of the semiconductor industry - which has guaranteed continued advance of computing power in the last 50 years - has ground to a halt in the past decade, new computational paradigms are being sought to remedy this dire situation. Quantum information technology is the new and ultimate frontier for signal processing and computing and leverages the unintuitive laws of our universe that hold on small scales. 50-100 qubit processors have been developed by Intel, IBM and Google, but quantum optical networks, needed to network them into "quantum data centers" in a way similar to their conventional analogues, are missing. This project aims to fill that gap by developing a new electronic-photonic chip technology and framework to allow creation of electronic-photonic quantum systems-on-chip (epQSoCs). epQSoCs combine light, electronic circuits, and quantum functions on a single microchip that can provide a widely deployable technology platform for quantum networks. The project will combine interdisciplinary expertise in photonics, electronic systems, and quantum communications to demonstrate the first epQSoC. A single-chip, "wall-plug" source of quantum correlated photon pairs, this epQSoC is a fundamental building block for more complex epQSoCs and for quantum networks. By integrating several components and novel capabilities never previously integrated in a single chip, this source will provide new levels of photon-pair source performance. The interdisciplinary project team will also educate a new generation of engineers in this emerging new technology area to foster innovation, excellence and global leadership in the United States.

A "wall plug" single-chip source of photon pairs, a fundamental building block of most quantum photonic systems, will be demonstrated having a high efficiency, rate and reconfigurability to produce factorizable quantum states and allow heralding of pure single photons. No such integrated device exists despite the fact that a rack-mounted fiber-nonlinearity-based source of this kind for lab use has been commercialized for almost a decade. The proposed project aims to change the quantum technology landscape with the demonstration of a fully integrated single-chip quantum pair source system. The chip photonic circuit will contain photonic elements for pre- and post-source linear pump filtering, a resonant nonlinear pair generator, pump pulse carver to allow active matching of the pump pulse length to the source's resonant bandwidth in order to control the produced photons joint spectral intensity (to yield a factorizable or other engineered biphoton states), and an ultra-low loss interface to fiber. The proposed approach addresses a number of challenges that arise in integration, on-chip filtering, and real-time control. In addition to standalone operation, the pair source will be the first implementation of an electronic-photonic quantum system-on-chip (epQSoC) and a key building block for more complex integrated quantum systems. The proposed epQSoCs will be implemented in a commercial 45nm CMOS electronic-photonic platform (with potential for integrating single-photon detectors on chip as well).
The project will create the technology framework (block libraries, tools, models and design methodologies) for low-cost, rapid innovation and design of sophisticated epQSoCs. This framework, along with associated educational materials and experiences will help create a new crop of engineers that are capable of tackling the complex, multidisciplinary nature of quantum information systems. Educational and outreach activities will provide exposure and training to a new generation of students and future leaders in this field, with special focus on underrepresented students.

This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

Our society is rapidly becoming reliant on neural networks based artificial intelligence computation. New algorithms are invented daily, increasing the memory and computational requirements for both inference and training. This explosive growth has created an enormous demand for distributed machine learning (ML) training and inference. Estimates by OpenAI illustrate the steady growth of computational requirements of 100x every two years since 2012, which is a 50x faster than the rate of computation improvements enabled previously through Moore?s Law of semiconductor industry that we have enjoyed in the last half-century. This new computation demand has been partly met by rapid development of hardware accelerators and software stacks to support these specialized computations. Hardware accelerators have provided a significant amount of speed-up but today?s training tasks can still take days and even weeks. The reason for this: as the number of workers (e.g. compute nodes) increases, the computation time per worker decreases, but the communication requirements between the nodes increase, creating a bottleneck in the interconnect between the compute nodes. Future distributed ML systems will require 1-2 orders of magnitude higher interconnect bandwidth per node, creating a pressing need for entirely new ways to build interconnects for distributed ML systems. This proposal aims to create a new paradigm for scaling distributed ML computation, by developing a scalable interconnect solution based on advancing the integrated electronics and photonics technology that enables direct node-to-node optical fiber connectivity. The proposed cross-stack collaborative multi-disciplinary work will enable the education and training of a unique crop of engineers and scientists that cross the boundaries of machine learning, networking, and electronic-photonic systems and devices, which are in severe demand. The principal investigators have an established track record of direct engagement with high-school students providing summer internships at Berkeley Wireless Research Center and MIT?s Women?s Technology Program, as well as exemplary undergraduate research activities at Boston University. The educational and outreach activities the PIs have put in place will ensure early exposure and continued training of new generation of leaders in this field, from K-12, through undergraduate and graduate studies, and continuing workforce education, with special focus on underrepresented students.

The interconnect has emerged as the key bottleneck in enabling the full potential of distributed ML. Future ML workloads are likely to require tens of Tbps of bandwidth per device. Ubiquitous deployment of logically-connected, physically distributed computation across shelf, rack and row scale can only be enabled by a new universal I/O that enables socket to socket communication at the energy, latency and bandwidth density of in-package interconnects. No such technology currently exists. Silicon-photonics based optical I/O has the potential to address this critical challenge, but fundamental advances?from chip manufacturing to routing algorithms?are still needed to ensure the scalability of these interconnect systems. To enable high-bandwidth density and energy-efficiency, dense wavelength division multiplexing must be used. High-efficiency ring resonator-based modulators and comb laser sources are needed to enable Tbps rates over each fiber connection and socket bandwidth scaling from 10s to 100s of Tbps. New link architectures like the proposed laser-forwarded coherent link are needed to enable high-efficiency external centralized comb laser sources with modest (sub-mW) power per wavelength per fiber port. The proposed work will also develop new scheduling algorithms, network architectures, and workload parallelism strategy to leverage the bandwidth density and low-latency of the universal optical I/O, to map large AI workloads with massive datasets to a scalable distributed compute system.

This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.