Vladimir Stojanovic, Ph.D. - US grants

Integrative, Hybrid and Complex Systems
Vladimir M. Stojanovic, Massachusetts Institute of Technology
Aleksandar Kavcic, University of Hawaii
Collaborative Research: Energy-efficient Communication with Optimized ECC Decoders: Connecting Algorithms and Implementations


Intellectual Merit: In a classical unidirectional communication system, the transmitter and the receiver functions are optimized separately. Recently, bidirectional, power-constrained communication systems have emerged, such as for wireless mobile devices and high-speed interconnections within digital systems, where both the transmitter and the receiver draw power from the same supply and where their joint power consumption affects the data rate and the energy-efficiency of the whole system. Thus, the transmitter and the receiver need to be jointly optimized. This research pursues a strategy to jointly optimize severely power-constrained communication systems to achieve a balance between speed (data rate), performance (in terms of error rate), and power consumption. The strategy uses special families of decoders of error correction codes (ECCs) that allow tradeoffs in complexity and power consumption for performance. The research considers the entire engineering design, from theoretical inception to very large-scale integration (VLSI) implementation, including the feedback loop from the VLSI design layer to the algorithm development layer.

Broader Impact: This research has the potential to reduce power consumption in wireless mobile communication, where battery life is critical, through an integrative approach. Results of this research will be incorporated into a communication system design course at MIT. Course material will be made freely available through MIT's OpenCourseWare (OCW) website. Similar course improvements are planned at the University of Hawaii.

The objective of this research is to develop low-power, robust, and energy-efficient sensors to satisfy a wide range of current applications including large-scale networks and implantable biomedical sensors. The aim is to develop the fundamental framework for sensor systems, connecting theory and algorithms with efficient hardware implementations and circuit metrics, such as power, footprint, quantization effects, and other circuit and channel non-idealities. The approach is to develop compressed sensing techniques that result in universal and efficient sensor designs.

Intellectual Merit: The transformative aspect of this research is a joint investigation into both theoretical and hardware development of compressed sensing techniques for sensor systems. The plan is to optimize energy allocation in the information chain, by shifting from (the original) randomization techniques to more energy-efficient deterministic sensing techniques. The focus is on regimes relevant to practice, and the results of this research are foreseen to greatly impact both systems and hardware communities.

Broader Impacts: Energy-efficient sensor nodes are in great demand today. For example in large-scale networks and implantable sensors, low power nodes are required to increase the average node life-time until maintenance, as well as improve the patient's quality of life. The goal is to convince practitioners, that compressed sensing can be mapped to hardware-efficient implementations. By creating an online portal, the project will also demonstrate the benefits of the developed sensing techniques to both experts and general population. To disseminate the fundamental systems/hardware framework, a new multi-disciplinary course will be created at MIT and offered to a wide-range of students.

Our society is on the cusp of a new revolution in integrated circuit technology and manufacturing. The new technology will successfully combine electronic and photonic systems creating previously unimagined functionality and performance. Such sophisticated electronic-photonic systems-on-chip with highly-efficient use of area, energy and spectral resources are critically needed in many communication scenarios. For example, current data-centers and high-performance supercomputers are both power-constrained. High-bandwidth density and high-energy efficiency photonic interconnects would allow the connectivity down to the processor chip level increasing the power-efficiency and utilization of the whole data-center, significantly impacting the national energy consumption in the next decade. However, the lack of large-scale integration approach, design methodology and unified cross-layer design has prevented the realization of these systems. The impact of the electronic-photonic designs and system design methodology proposed in this project spans not only communication systems, but also a variety of other sophisticated electronic-photonic systems (e.g. detection, sensing, and instrumentation). The multi-disciplinary work will educate a unique crop of engineers and scientists that cross the boundaries of electronic and photonic systems.

The objective of the research project is to utilize recently developed large-scale electronic-photonic integration approaches to design short-reach coherent-modulation photonic links that significantly improve the area, energy and spectral-efficiency. The proposed electronic-photonic circuit topologies for coherent high-order modulation transmitters and receivers leverage the advantages of each domain and correct for the non-idealities in the other. Starting from the modeling and simulation infrastructure, the proposed research comprises a unique simulation and modeling framework in Verilog-A, which allows for true co-simulation of photonic and electronic circuits, under large signal, non-linear, time-varying conditions. This capability gives vital insights into the interaction of electronic and photonic circuits. It is essential for the use of the resonant components as the second key ingredient in designing efficient electronic-photonic communication systems. Although energy and area efficient, the resonant components require sophisticated wavelength stabilization loops and electronic drive to compensate for their transfer-function characteristics, which are enabled by the co-simulation methodology and abundance of high-performance transistors in the proposed integration approaches.

Our society is rapidly becoming reliant on neural networks based artificial intelligence computation. New algorithms are invented daily, increasing the memory and computational requirements for both inference and training. This explosive growth has created an enormous demand for distributed machine learning (ML) training and inference. Estimates by OpenAI illustrate the steady growth of computational requirements of 100x every two years since 2012, which is a 50x faster than the rate of computation improvements enabled previously through Moore?s Law of semiconductor industry that we have enjoyed in the last half-century. This new computation demand has been partly met by rapid development of hardware accelerators and software stacks to support these specialized computations. Hardware accelerators have provided a significant amount of speed-up but today?s training tasks can still take days and even weeks. The reason for this: as the number of workers (e.g. compute nodes) increases, the computation time per worker decreases, but the communication requirements between the nodes increase, creating a bottleneck in the interconnect between the compute nodes. Future distributed ML systems will require 1-2 orders of magnitude higher interconnect bandwidth per node, creating a pressing need for entirely new ways to build interconnects for distributed ML systems. This proposal aims to create a new paradigm for scaling distributed ML computation, by developing a scalable interconnect solution based on advancing the integrated electronics and photonics technology that enables direct node-to-node optical fiber connectivity. The proposed cross-stack collaborative multi-disciplinary work will enable the education and training of a unique crop of engineers and scientists that cross the boundaries of machine learning, networking, and electronic-photonic systems and devices, which are in severe demand. The principal investigators have an established track record of direct engagement with high-school students providing summer internships at Berkeley Wireless Research Center and MIT?s Women?s Technology Program, as well as exemplary undergraduate research activities at Boston University. The educational and outreach activities the PIs have put in place will ensure early exposure and continued training of new generation of leaders in this field, from K-12, through undergraduate and graduate studies, and continuing workforce education, with special focus on underrepresented students.

The interconnect has emerged as the key bottleneck in enabling the full potential of distributed ML. Future ML workloads are likely to require tens of Tbps of bandwidth per device. Ubiquitous deployment of logically-connected, physically distributed computation across shelf, rack and row scale can only be enabled by a new universal I/O that enables socket to socket communication at the energy, latency and bandwidth density of in-package interconnects. No such technology currently exists. Silicon-photonics based optical I/O has the potential to address this critical challenge, but fundamental advances?from chip manufacturing to routing algorithms?are still needed to ensure the scalability of these interconnect systems. To enable high-bandwidth density and energy-efficiency, dense wavelength division multiplexing must be used. High-efficiency ring resonator-based modulators and comb laser sources are needed to enable Tbps rates over each fiber connection and socket bandwidth scaling from 10s to 100s of Tbps. New link architectures like the proposed laser-forwarded coherent link are needed to enable high-efficiency external centralized comb laser sources with modest (sub-mW) power per wavelength per fiber port. The proposed work will also develop new scheduling algorithms, network architectures, and workload parallelism strategy to leverage the bandwidth density and low-latency of the universal optical I/O, to map large AI workloads with massive datasets to a scalable distributed compute system.

This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.