Rupesh S. Shelar, Ph.D.
Affiliations: | 2004 | University of Minnesota, Twin Cities, Minneapolis, MN |
Area:
Electronics and Electrical EngineeringGoogle:
"Rupesh Shelar"Parents
Sign in to add mentor| Sachin Sapatnekar | grad student | 2004 | UMN | |
| (Synthesis for nanometer technologies.) | ||||
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Publications
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| Shelar RS, Patyra M. (2013) Impact of local interconnects on timing and power in a high performance microprocessor Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 32: 1623-1627 |
| Shelar RS. (2012) A fast and near-optimal clustering algorithm for low-power clock tree synthesis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 1781-1786 |
| Liu Y, Shelar RS, Hu J. (2011) Simultaneous technology mapping and placement for delay minimization Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 30: 416-426 |
| Shelar RS. (2010) Routing with constraints for post-grid clock distribution in microprocessors Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 245-249 |
| Shelar RS. (2009) An algorithm for routing with capacitance/distance constraints for clock distribution in microprocessors Proceedings of the International Symposium On Physical Design. 141-147 |
| Yifang L, Shelar RS, Jiang H. (2008) Delay-optimal simultaneous technology mapping and placement with applications to timing optimization Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 101-106 |
| Shelar RS. (2007) An efficent clustering algorithm for low power clock tree synthesis Proceedings of the International Symposium On Physical Design. 181-188 |
| Shelar RS, Saxena P, Sapatnekar SS. (2006) Technology mapping algorithm targeting routing congestion under delay constraints Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 625-635 |
| Shelar RS, Sapatnekar SS. (2005) BDD decomposition for delay oriented pass transistor logic synthesis Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 13: 957-970 |
| Shelar RS, Sapatnekar SS, Saxena P, et al. (2005) A predictive distributed congestion metric with application to technology mapping Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 696-709 |