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Rupesh S. Shelar, Ph.D. - Publications

Affiliations: 
2004 University of Minnesota, Twin Cities, Minneapolis, MN 
Area:
Electronics and Electrical Engineering
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14 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2013 Shelar RS, Patyra M. Impact of local interconnects on timing and power in a high performance microprocessor Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 32: 1623-1627. DOI: 10.1109/Tcad.2013.2266404  0.433
2012 Shelar RS. A fast and near-optimal clustering algorithm for low-power clock tree synthesis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 1781-1786. DOI: 10.1109/Tcad.2012.2206592  0.503
2011 Liu Y, Shelar RS, Hu J. Simultaneous technology mapping and placement for delay minimization Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 30: 416-426. DOI: 10.1109/Tcad.2010.2089569  0.625
2010 Shelar RS. Routing with constraints for post-grid clock distribution in microprocessors Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 245-249. DOI: 10.1109/Tcad.2009.2040012  0.514
2009 Shelar RS. An algorithm for routing with capacitance/distance constraints for clock distribution in microprocessors Proceedings of the International Symposium On Physical Design. 141-147. DOI: 10.1145/1514932.1514964  0.466
2008 Yifang L, Shelar RS, Jiang H. Delay-optimal simultaneous technology mapping and placement with applications to timing optimization Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 101-106. DOI: 10.1109/ICCAD.2008.4681558  0.576
2007 Shelar RS. An efficent clustering algorithm for low power clock tree synthesis Proceedings of the International Symposium On Physical Design. 181-188. DOI: 10.1145/1231996.1232037  0.414
2006 Shelar RS, Saxena P, Sapatnekar SS. Technology mapping algorithm targeting routing congestion under delay constraints Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 625-635. DOI: 10.1109/Tcad.2006.870078  0.596
2005 Shelar RS, Sapatnekar SS. BDD decomposition for delay oriented pass transistor logic synthesis Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 13: 957-970. DOI: 10.1109/Tvlsi.2005.853601  0.607
2005 Shelar RS, Sapatnekar SS, Saxena P, Wang X. A predictive distributed congestion metric with application to technology mapping Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 696-709. DOI: 10.1109/Tcad.2005.846368  0.568
2005 Shelar RS, Wang X, Saxena P, Sapatnekar SS. An efficient technology mapping algorithm targeting routing congestion under delay constraints Proceedings of the International Symposium On Physical Design. 137-144.  0.588
2004 Shelar RS, Sapatnekar SS, Saxena P, Wang X. A predictive distributed congestion metric and its application to technology mapping Proceedings of the International Symposium On Physical Design. 210-217.  0.452
2002 Shelar RS, Sapatnekar SS. An efficient algorithm for low power pass transistor logic synthesis Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference On Vlsi Design, Asp-Dac/Vlsi Design 2002. 87-92. DOI: 10.1109/ASPDAC.2002.994890  0.581
2001 Shelar RS, Sapatnekar SS. Recursive bipartitioning of BDDs for performance driven synthesis of pass transistor logic circuits Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 449-452.  0.567
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