Year |
Citation |
Score |
2013 |
Kaviani K, Amirkhany A, Huang C, Le P, Beyene WT, Madden C, Saito K, Sano K, Murugan VI, Chang KYK, Yuan XC. A 0.4-mW/Gb/s near-ground receiver front-end with replica transconductance termination calibration for a 16-Gb/s source-series terminated transceiver Ieee Journal of Solid-State Circuits. 48: 636-648. DOI: 10.1109/Jssc.2013.2242714 |
0.603 |
|
2012 |
Kaviani K, Wu T, Wei J, Amirkhany A, Shen J, Chin TJ, Thakkar C, Beyene WT, Chan N, Chen C, Chuang BR, Dressler D, Gadde VP, Hekmat M, Ho E, et al. A Tri-modal 20-Gbps/link differential/DDR3/GDDR5 memory interface Ieee Journal of Solid-State Circuits. 47: 926-937. DOI: 10.1109/Jssc.2012.2185370 |
0.498 |
|
2011 |
Amirkhany A, Wei J, Mishra N, Shen J, Beyene W, Chin T, Huang C, Gadde V, Kaviani K, Le P, M M, Madden C, Mukherjee S, Raghavan L, Saito K, et al. A 12.8-Gb/s/link tri-modal single-ended memory interface for graphics applications Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 232-233. DOI: 10.1109/Jssc.2012.2185369 |
0.476 |
|
2010 |
Aryanfar F, Amirkhany A. A low-cost resonance mitigation technique for multidrop memory interfaces Ieee Transactions On Circuits and Systems Ii: Express Briefs. 57: 339-342. DOI: 10.1109/Tcsii.2010.2047306 |
0.353 |
|
2010 |
Ahmadi MR, Amirkhany A, Harjani R. A 5 Gbps 0.13 μm CMOS pilot-based clock and data recovery scheme for high-speed links Ieee Journal of Solid-State Circuits. 45: 1533-1541. DOI: 10.1109/Jssc.2010.2047439 |
0.434 |
|
2008 |
Savoj J, Abbasfar A, Amirkhany A, Jeeradit M, Garlepp BW. A 12-GS/s phase-calibrated CMOS digital-to-analog converter for backplane communications Ieee Journal of Solid-State Circuits. 43: 1207-1215. DOI: 10.1109/Jssc.2008.920319 |
0.53 |
|
2008 |
Amirkhany A, Abbasfar A, Savoj J, Jeeradit M, Garlepp B, Kollipara RT, Stojanovic V, Horowitz M. A 24 Gb/s software programmable analog multi-tone transmitter Ieee Journal of Solid-State Circuits. 43: 999-1008. DOI: 10.1109/Jssc.2008.917520 |
0.339 |
|
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