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Timothy Sherwood - Publications

Affiliations: 
Computer Science University of California, Santa Barbara, Santa Barbara, CA, United States 
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38 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Cui W, Tzimpragos G, Tao Y, Mcmahan J, Dangwal D, Tsiskaridze N, Michelogiannakis G, Vasudevan DP, Sherwood T. Language Support for Navigating Architecture Design in Closed Form Acm Journal On Emerging Technologies in Computing Systems. 16: 1-28. DOI: 10.1145/3360047  0.319
2020 Dangwal D, Tzimpragos G, Sherwood T. Agile Hardware Development and Instrumentation With PyRTL Ieee Micro. 40: 76-84. DOI: 10.1109/Mm.2020.2997704  0.424
2020 Dangwal D, Cui W, McMahan J, Sherwood T. Trace Wringing for Program Trace Privacy Ieee Micro. 40: 108-115. DOI: 10.1109/Mm.2020.2986113  0.377
2018 Madhavan A, Sherwood T, Strukov DB. High-Throughput Pattern Matching With CMOL FPGA Circuits: Case for Logic-in-Memory Computing Ieee Transactions On Very Large Scale Integration Systems. 26: 2759-2772. DOI: 10.1109/Tvlsi.2018.2809644  0.422
2018 Mao B, Hu W, Althoff A, Matai J, Tai Y, Mu D, Sherwood T, Kastner R. Quantitative Analysis of Timing Channel Security in Cryptographic Hardware Design Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 1719-1732. DOI: 10.1109/Tcad.2017.2768420  0.441
2018 McMahan J, Christensen M, Nichols L, Roesch J, Guo S, Hardekopf B, Sherwood T. An Architecture for Analysis Ieee Micro. 38: 107-115. DOI: 10.1109/Mm.2018.032271067  0.396
2015 Madhavan A, Sherwood T, Strukov D. Race Logic: Abusing Hardware Race Conditions to Perform Useful Computation Ieee Micro. 35: 48-57. DOI: 10.1109/Mm.2015.43  0.413
2014 Hu W, Mu D, Oberg J, Mao B, Tiwari M, Sherwood T, Kastner R. Gate-level information flow tracking for security lattices Acm Transactions On Design Automation of Electronic Systems. 20. DOI: 10.1145/2676548  0.658
2014 Oberg J, Meiklejohn S, Sherwood T, Kastner R. Leveraging gate-level properties to identify hardware timing channels Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 33: 1288-1301. DOI: 10.1109/Tcad.2014.2331332  0.412
2014 Wassel HMG, Gao Y, Oberg JK, Huffmire T, Kastner R, Chong FT, Sherwood T. Networks on chip with provable security properties Ieee Micro. 34: 57-68. DOI: 10.1109/Mm.2014.46  0.788
2013 Valamehr J, Sherwood T, Kastner R, Marangoni-Simonsen D, Huffmire T, Irvine C, Levin T. A 3-D split manufacturing approach to trustworthy system development Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 32: 611-615. DOI: 10.1109/Tcad.2012.2227257  0.755
2013 Valamehr JK, Chase M, Kamara S, Putnam A, Shumow D, Vaikuntanathan V, Sherwood T. Inspection-resistant memory architectures Ieee Micro. 33: 48-56. DOI: 10.1109/Mm.2013.27  0.797
2013 Oberg J, Sherwood T, Kastner R. Eliminating Timing Information Flows in a Mix-Trusted System-on-Chip Ieee Design & Test of Computers. 30: 55-62. DOI: 10.1109/Mdt.2013.2247457  0.423
2012 Mazloom B, Mysore S, Tiwari M, Agrawal B, Sherwood T. Dataflow tomography: Information flow tracking for understanding and visualizing full systems Transactions On Architecture and Code Optimization. 9. DOI: 10.1145/2133382.2133385  0.744
2012 Hu W, Oberg J, Irturk A, Tiwari M, Sherwood T, Mu D, Kastner R. On the complexity of generating gate level information flow tracking logic Ieee Transactions On Information Forensics and Security. 7: 1067-1080. DOI: 10.1109/Tifs.2012.2189105  0.663
2012 Wassel HMG, Dai D, Tiwari M, Valamehr JK, Theogarajan L, Dionne J, Chong FT, Sherwood T. Opportunities and challenges of using plasmonic components in nanophotonic architectures Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 2: 154-168. DOI: 10.1109/Jetcas.2012.2193934  0.767
2012 Trujillo-Olaya V, Sherwood T, Koç ÇK. Analysis of performance versus security in hardware realizations of small elliptic curves for lightweight applications Journal of Cryptographic Engineering. 2: 179-188. DOI: 10.1007/S13389-012-0039-X  0.464
2011 Hu W, Oberg J, Irturk A, Tiwari M, Sherwood T, Mu D, Kastner R. Theoretical fundamentals of gate level information flow tracking Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 30: 1128-1140. DOI: 10.1109/Tcad.2011.2120970  0.604
2010 Huffmire T, Levin T, Nguyen T, Irvine C, Brotherton B, Wang G, Sherwood T, Kastner R. Security Primitives for Reconfigurable Hardware-Based Systems Acm Transactions On Reconfigurable Technology and Systems. 3: 10. DOI: 10.1145/1754386.1754391  0.814
2010 Tiwari M, Li X, Wassel HMG, Mazloom B, Mysore S, Chong FT, Sherwood T. Gate-level information-flow tracking for secure architectures Ieee Micro. 30: 92-100. DOI: 10.1109/Mm.2010.17  0.748
2009 Kataria N, Brewer F, Hespanha J, Sherwood T. Metric based multi-timescale control for reducing power in embedded systems Journal of Low Power Electronics. 5: 354-362. DOI: 10.1166/Jolpe.2009.1035  0.363
2009 Dixon R, Eğecioğlu Ö, Sherwood T. Analysis Of Bit-Split Languages For Packet Scanning And Experiments With Wildcard Matching International Journal of Foundations of Computer Science. 20: 597-612. DOI: 10.1142/S0129054109006760  0.513
2009 Agrawal B, Sherwood T. High-bandwidth network memory system through virtual pipelines Ieee Acm Transactions On Networking. 17: 1029-1041. DOI: 10.1109/Tnet.2008.2008646  0.634
2008 Mysore S, Agrawal B, Neuber R, Sherwood T, Shrivastava N, Suri S. Formulating and implementing profiling over adaptive ranges Transactions On Architecture and Code Optimization. 5. DOI: 10.1145/1369396.1369398  0.753
2008 Huffmire T, Brotherton B, Callegari N, Valamehr J, White J, Kastner R, Sherwood T. Designing secure systems on reconfigurable hardware Acm Transactions On Design Automation of Electronic Systems. 13. DOI: 10.1145/1367045.1367053  0.776
2008 Hoover G, Brewer F, Sherwood T. Structural integrity: safety in miniature technology Acm Sigbed Review. 5: 14. DOI: 10.1145/1366283.1366297  0.405
2008 Agrawal B, Sherwood T. Ternary CAM Power and Delay Model: Extensions and Uses Ieee Transactions On Very Large Scale Integration Systems. 16: 554-564. DOI: 10.1109/Tvlsi.2008.917538  0.607
2008 Huffmire T, Brotherton B, Sherwood T, Kastner R, Levin T, Nguyen TD, Irvine C. Managing Security in FPGA-Based Embedded Systems Ieee Design & Test of Computers. 25: 590-598. DOI: 10.1109/Mdt.2008.166  0.802
2008 Huffmire T, Sherwood T, Kastner R, Levin T. Enforcing memory policy specifications in reconfigurable hardware Computers & Security. 27: 197-215. DOI: 10.1016/J.Cose.2008.05.002  0.797
2007 Mysore S, Agrawal B, Srivastava N, Lin S, Banerjee K, Sherwood T. 3D Integration for Introspection Ieee Micro. 27: 77-83. DOI: 10.1109/Mm.2007.1  0.757
2006 Nagpurkar P, Mousa H, Krintz C, Sherwood T. Efficient remote profiling for resource-constrained devices Acm Transactions On Architecture and Code Optimization. 3: 35-66. DOI: 10.1145/1132462.1132465  0.607
2006 Tan L, Brotherton B, Sherwood T. Bit-split string-matching engines for intrusion detection and prevention Acm Transactions On Architecture and Code Optimization. 3: 3-34. DOI: 10.1145/1132462.1132464  0.411
2006 Tan L, Sherwood T. Architectures for Bit-Split String Scanning in Intrusion Detection Ieee Micro. 26: 110-117. DOI: 10.1109/Mm.2006.5  0.372
2005 Meng Y, Gong W, Kastner R, Sherwood T. Algorithm/Architecture Co-exploration for Designing Energy Efficient Wireless Channel Estimator Journal of Low Power Electronics. 1: 238-248. DOI: 10.1166/Jolpe.2005.049  0.518
2005 Shayesteh A, Reinman G, Jouppi N, Sair S, Sherwood T. Dynamically configurable shared CMP helper engines for improved performance Acm Sigarch Computer Architecture News. 33: 70-79. DOI: 10.1145/1105734.1105744  0.346
2005 Meng Y, Sherwood T, Kastner R. Exploring the limits of leakage power reduction in caches Acm Transactions On Architecture and Code Optimization. 2: 221-246. DOI: 10.1145/1089008.1089009  0.488
2003 Sair S, Sherwood T, Calder B. A decoupled predictor-directed stream prefetching architecture Ieee Transactions On Computers. 52: 260-276. DOI: 10.1109/Tc.2003.1183943  0.381
2001 Mahlke S, Ravindran R, Schlansker M, Schreiber R, Sherwood T. Bitwidth cognizant architecture synthesis of custom hardware accelerators Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 20: 1355-1371. DOI: 10.1109/43.959864  0.39
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