| Year |
Citation |
Score |
| 2016 |
Sengupta D, Mishra V, Sapatnekar SS. Invited - Optimizing device reliability effects at the intersection of physics, circuits, and architecture Proceedings - Design Automation Conference. 5. DOI: 10.1145/2897937.2905016 |
0.335 |
|
| 2014 |
Boghrati B, Sapatnekar SS. Incremental analysis of power grids using backward random walks Acm Transactions On Design Automation of Electronic Systems. 19. DOI: 10.1145/2611763 |
0.783 |
|
| 2014 |
Fang J, Sapatnekar SS. Incorporating hot-carrier injection effects into timing analysis for large circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 22: 2738-2751. DOI: 10.1109/Tvlsi.2013.2296499 |
0.566 |
|
| 2014 |
Gupta S, Sapatnekar SS. Variation-aware variable latency design Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 22: 1106-1117. DOI: 10.1109/Tvlsi.2013.2265662 |
0.541 |
|
| 2013 |
Gupta S, Sapatnekar SS. Employing circadian rhythms to enhance power and reliability Acm Transactions On Design Automation of Electronic Systems. 18. DOI: 10.1145/2491477.2491482 |
0.541 |
|
| 2013 |
Mishra V, Sapatnekar SS. The impact of electromigration in copper interconnects on power grid integrity Proceedings - Design Automation Conference. DOI: 10.1145/2463209.2488842 |
0.344 |
|
| 2013 |
Sapatnekar SS. What happens when circuits grow old: Aging issues in CMOS design 2013 International Symposium On Vlsi Technology, Systems and Application, Vlsi-Tsa 2013. DOI: 10.1109/VLSI-TSA.2013.6545621 |
0.364 |
|
| 2013 |
Fang J, Sapatnekar SS. The impact of BTI variations on timing in digital logic circuits Ieee Transactions On Device and Materials Reliability. 13: 277-286. DOI: 10.1109/Tdmr.2013.2237910 |
0.568 |
|
| 2012 |
Gupta S, Sapatnekar SS. Compact current source models for timing analysis under temperature and body bias variations Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 20: 2104-2117. DOI: 10.1109/Tvlsi.2011.2169686 |
0.536 |
|
| 2012 |
Fang J, Sapatnekar SS. Scalable methods for analyzing the circuit failure probability due to gate oxide breakdown Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 20: 1960-1973. DOI: 10.1109/Tvlsi.2011.2166568 |
0.552 |
|
| 2012 |
Gupta S, Sapatnekar SS. BTI-aware design using variable latency units Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 775-780. DOI: 10.1109/ASPDAC.2012.6165059 |
0.314 |
|
| 2012 |
Fang J, Sapatnekar SS. The impact of hot carriers on timing in large circuits Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 591-596. DOI: 10.1109/ASPDAC.2012.6165025 |
0.316 |
|
| 2012 |
Boghrati B, Sapatnekar SS. Incremental power network analysis using backward random walks Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 41-46. DOI: 10.1109/ASPDAC.2012.6164983 |
0.782 |
|
| 2011 |
Sapatnekar SS. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems: Editorial Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 30: 1. DOI: 10.1109/TCAD.2010.2097013 |
0.302 |
|
| 2011 |
Sapatnekar S, Zhou P, Sridharan K. Power Grid Optimization in 3D Circuits Using MIM and CMOS Decoupling Capacitors Ieee Design & Test of Computers. DOI: 10.1109/Mdt.2009.99 |
0.558 |
|
| 2011 |
Sapatnekar SS. Overcoming variations in nanometer-scale technologies Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 1: 5-18. DOI: 10.1109/JETCAS.2011.2138250 |
0.34 |
|
| 2011 |
Fang J, Sapatnekar SS. Accounting for inherent circuit resilience and process variations in analyzing gate oxide reliability Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 689-694. DOI: 10.1109/ASPDAC.2011.5722275 |
0.324 |
|
| 2011 |
Boghrati B, Sapatnekar S. A scaled random walk solver for fast power grid analysis Proceedings -Design, Automation and Test in Europe, Date. 38-43. |
0.776 |
|
| 2010 |
Wei Y, Sapatnekar SS. Dummy fill optimization for enhanced manufacturability Proceedings of the International Symposium On Physical Design. 97-104. DOI: 10.1145/1735023.1735051 |
0.302 |
|
| 2010 |
Liu Q, Sapatnekar SS. Capturing post-silicon variations using a representative critical path Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 211-222. DOI: 10.1109/Tcad.2009.2035552 |
0.561 |
|
| 2010 |
Qian H, Sapatnekar SS. Fast poisson solvers for thermal analysis Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 698-702. DOI: 10.1109/ICCAD.2010.5654249 |
0.476 |
|
| 2010 |
Boghrati B, Sapatnekar S. Incremental solution of power grids using random walks Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 757-762. DOI: 10.1109/ASPDAC.2010.5419787 |
0.749 |
|
| 2009 |
Sapatnekar SS. Technical perspective: Where the chips may fall Communications of the Acm. 52: 94. DOI: 10.1145/1536616.1536640 |
0.378 |
|
| 2009 |
Liu Q, Sapatnekar SS. Synthesizing a representative critical path for post-silicon delay prediction Proceedings of the International Symposium On Physical Design. 183-190. DOI: 10.1145/1514932.1514973 |
0.374 |
|
| 2009 |
Liu Q, Sapatnekar SS. A framework for scalable postsilicon statistical delay prediction under process variations Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 1201-1212. DOI: 10.1109/Tcad.2009.2021732 |
0.484 |
|
| 2009 |
Sapatnekar SS. Addressing thermal and power delivery bottlenecks in 3D circuits Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 423-428. DOI: 10.1109/ASPDAC.2009.4796518 |
0.34 |
|
| 2008 |
Sapatnekar SS. Variability and statistical design Ipsj Transactions On System Lsi Design Methodology. 1: 18-32. DOI: 10.2197/ipsjtsldm.1.18 |
0.33 |
|
| 2008 |
Zhan Y, Sapatnekar SS. Automated module assignment in stacked-Vdd designs for high-efficiency power delivery Acm Journal On Emerging Technologies in Computing Systems. 4. DOI: 10.1145/1412587.1412591 |
0.587 |
|
| 2008 |
Keane J, Eom H, Kim T, Sapatnekar S, Kim C. Stack Sizing for Optimal Current Drivability in Subthreshold Circuits Ieee Transactions On Very Large Scale Integration Systems. 16: 598-602. DOI: 10.1109/Tvlsi.2008.917571 |
0.471 |
|
| 2008 |
Gu J, Keane J, Sapatnekar S, Kim CH. Statistical leakage estimation of double gate FinFET devices considering the width quantization property Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 16: 206-209. DOI: 10.1109/Tvlsi.2007.909809 |
0.357 |
|
| 2008 |
Karandikar SK, Sapatnekar SS. Technology mapping using logical effort for solving the load-distribution problem Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 45-58. DOI: 10.1109/TCAD.2007.907067 |
0.8 |
|
| 2008 |
Sapatnekar S. Building your yield of dreams [review of Design for Manufacturability and Yield for Nano-Scale CMOS by Charles Chiang and Jamil Kawa; 2007] Ieee Design & Test of Computers. 25: 194-195. DOI: 10.1109/Mdt.2008.31 |
0.352 |
|
| 2008 |
Sapatnekar S. Adapting to the times [review of Adaptive Techniques for Dynamic Processor Optimization: Theory and Practice (Wang, A. and Naffziger, S., Eds.; 2008)] Ieee Design & Test of Computers. 25: 496-497. DOI: 10.1109/Mdt.2008.125 |
0.342 |
|
| 2007 |
Sapatnekar SS. Computer-aided design of 3d integrated circuits Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 317. DOI: 10.1145/1228784.1228788 |
0.346 |
|
| 2007 |
Qian H, Sapatnekar SS. Stochastic preconditioning for diagonally dominant matrices Siam Journal On Scientific Computing. 30: 1178-1204. DOI: 10.1137/07068713X |
0.41 |
|
| 2007 |
Zhan Y, Sapatnekar SS. High-efficiency green function-based thermal simulation algorithms Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 1661-1675. DOI: 10.1109/Tcad.2007.895754 |
0.545 |
|
| 2007 |
Yong Z, Tianpei Z, Sapatnekar SS. Module assignment for pin-limited designs under the stacked-Vdd paradigm Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 656-659. DOI: 10.1109/ICCAD.2007.4397340 |
0.369 |
|
| 2007 |
Bufistov D, Cortadella J, Kishinevsky M, Sapatnekar S. A general model for performance optimization of sequential systems Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 362-369. DOI: 10.1109/ICCAD.2007.4397291 |
0.311 |
|
| 2007 |
Goplen B, Sapatnekar S. Placement of 3D ICs with thermal and interlayer via considerations Proceedings - Design Automation Conference. 626-631. DOI: 10.1109/DAC.2007.375239 |
0.7 |
|
| 2007 |
Sapatnekar SS. CAD for 3D circuits: Solutions and challenges 2007 Proceedings - 24th International Vlsi Multilevel Interconnection Conference, Vmic 2007. 245-252. |
0.31 |
|
| 2006 |
Shelar RS, Saxena P, Sapatnekar SS. Technology mapping algorithm targeting routing congestion under delay constraints Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 625-635. DOI: 10.1109/Tcad.2006.870078 |
0.778 |
|
| 2006 |
Singh J, Sapatnekar SS. Partition-based algorithm for power grid design using locality Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 664-677. DOI: 10.1109/TCAD.2006.870071 |
0.31 |
|
| 2006 |
Goplen B, Sapatnekar SS. Placement of thermal vias in 3-D ICs using various thermal objectives Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 692-708. DOI: 10.1109/Tcad.2006.870069 |
0.677 |
|
| 2006 |
Gu J, Keane J, Sapatnekar S, Kim C. Width quantization aware FinFET circuit design Proceedings of the Custom Integrated Circuits Conference. 337-340. DOI: 10.1109/CICC.2006.320916 |
0.303 |
|
| 2006 |
Zhan Y, Goplen B, Sapatnekar SS. Electrothermal analysis and optimization techniques for nanoscale integrated circuits Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 2006: 219-222. |
0.725 |
|
| 2005 |
Sapatnekar S. What is statistical design Acm Sigda Newsletter. 35: 1. DOI: 10.1145/1113784.1113786 |
0.459 |
|
| 2005 |
Karandikar SK, Sapatnekar SS. Fast comparisons of circuit implementations Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 13: 1329-1339. DOI: 10.1109/Tvlsi.2005.862727 |
0.803 |
|
| 2005 |
Shelar RS, Sapatnekar SS. BDD decomposition for delay oriented pass transistor logic synthesis Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 13: 957-970. DOI: 10.1109/Tvlsi.2005.853601 |
0.795 |
|
| 2005 |
Chang H, Sapatnekar SS. Statistical timing analysis under spatial correlations Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 1467-1482. DOI: 10.1109/Tcad.2005.850834 |
0.604 |
|
| 2005 |
Singh J, Sapatnekar SS. Congestion-aware topology optimization of structured power/ground networks Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 683-695. DOI: 10.1109/TCAD.2005.846369 |
0.319 |
|
| 2005 |
Ababei C, Feng Y, Goplen B, Mogal H, Zhang T, Bazargan K, Sapatnekar S. Placement and routing in 3D integrated circuits Ieee Design and Test of Computers. 22: 520-531. DOI: 10.1109/Mdt.2005.150 |
0.757 |
|
| 2005 |
Sapatnekar S, Nowka K. Guest editors' introduction: New dimensions in 3D integration Ieee Design and Test of Computers. 22: 496-497. DOI: 10.1109/Mdt.2005.142 |
0.303 |
|
| 2005 |
Sapatnekar S. Designing "Vary" Good Circuitry Ieee Design & Test of Computers. 22: 596-597. DOI: 10.1109/Mdt.2005.137 |
0.319 |
|
| 2005 |
Karandikar SK, Sapatnekar SS. Fast estimation of area-delay trade-offs in circuit sizing Proceedings - Ieee International Symposium On Circuits and Systems. 3575-3578. DOI: 10.1109/ISCAS.2005.1465402 |
0.805 |
|
| 2005 |
Nookala V, Sapatnekar SS. Designing optimized pipelined global interconnects: Algorithms and methodology impact Proceedings - Ieee International Symposium On Circuits and Systems. 608-611. DOI: 10.1109/ISCAS.2005.1464661 |
0.813 |
|
| 2005 |
Qian H, Sapatnekar SS. A hybrid linear equation solver and its application in quadratic placement Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 2005: 904-908. DOI: 10.1109/ICCAD.2005.1560190 |
0.423 |
|
| 2005 |
Zhan Y, Sapatnekar SS. A high efficiency full-chip thermal simulation algorithm Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 2005: 634-637. DOI: 10.1109/ICCAD.2005.1560144 |
0.544 |
|
| 2005 |
Zhang T, Sapatnekar SS. Buffering global interconnects in structured ASIC design Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 1: 23-26. DOI: 10.1016/J.Vlsi.2007.04.002 |
0.494 |
|
| 2005 |
Goplen B, Sapatnekar S. Thermal via placement in 3D ICs Proceedings of the International Symposium On Physical Design. 167-174. |
0.681 |
|
| 2005 |
Sapatnekar S, Roychowdhury J, Harjani R. Tutorial: High-speed interconnect technology: On-chip and off-chip Proceedings of the Ieee International Conference On Vlsi Design. 7. |
0.371 |
|
| 2005 |
Singh J, Sapatnekar SS. A fast algorithm for power grid design Proceedings of the International Symposium On Physical Design. 70-77. |
0.303 |
|
| 2005 |
Goplen B, Saxena P, Sapatnekar S. Net weighting to reduce repeater counts during placement Proceedings - Design Automation Conference. 503-508. |
0.655 |
|
| 2004 |
Karandikar SK, Sapatnekar SS. Logical effort based technology mapping Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 419-422. DOI: 10.1109/ICCAD.2004.1382611 |
0.804 |
|
| 2004 |
Nookala V, Sapatnekar SS. A method for correcting the functionality of a wire-pipelined circuit Proceedings - Design Automation Conference. 570-575. |
0.807 |
|
| 2004 |
Singh J, Sapatnekar SS. Topology optimization of structured power/ground networks Proceedings of the International Symposium On Physical Design. 116-123. |
0.305 |
|
| 2004 |
Chang H, Qian H, Sapatnekar SS. The certainty of uncertainty: Randomness in nanometer design Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 3254: 36-47. |
0.309 |
|
| 2003 |
Goplen B, Sapatnekar S. Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 86-89. |
0.685 |
|
| 2003 |
Rajappan V, Sapatnekar SS. An efficient algorithm for calculating the worst-case delay due to crosstalk Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 76-81. |
0.336 |
|
| 2002 |
Ketkar M, Sapatnekar SS. Standby power optimization via transistor sizing and dual threshold voltage assignment Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 375-378. DOI: 10.1145/774572.774628 |
0.312 |
|
| 2002 |
Zhao M, Sapatnekar SS. Technology mapping algorithms for domino logic Acm Transactions On Design Automation of Electronic Systems. 7: 306-335. DOI: 10.1145/544536.544541 |
0.313 |
|
| 2002 |
Hu J, Sapatnekar SS. A timing-constrained simultaneous global routing algorithm Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 21: 1025-1036. DOI: 10.1109/Tcad.2002.801083 |
0.491 |
|
| 2002 |
Shelar RS, Sapatnekar SS. An efficient algorithm for low power pass transistor logic synthesis Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference On Vlsi Design, Asp-Dac/Vlsi Design 2002. 87-92. DOI: 10.1109/ASPDAC.2002.994890 |
0.788 |
|
| 2002 |
Sapatnekar SS, Wong MDF. IEEE Transactions on Computer-Aided Design of Integrated Circuits and System: Guest editorial Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 21: 1-2. DOI: 10.1109/43.974132 |
0.339 |
|
| 2002 |
Su H, Sapatnekar SS, Nassif SR. An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts Proceedings of the International Symposium On Physical Design. 68-73. |
0.33 |
|
| 2001 |
Karandikar SK, Sapatnekar SS. Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect Proceedings - Design Automation Conference. 377-382. DOI: 10.1109/TVLSI.2003.817137 |
0.797 |
|
| 2001 |
Hu J, Sapatnekar SS. Performance driven global routing through gradual refinement Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 481-483. DOI: 10.1080/1065514021000012219 |
0.509 |
|
| 2001 |
Hu J, Sapatnekar SS. A survey on multi-net global routing for integrated circuits Integration, the Vlsi Journal. 31: 1-49. DOI: 10.1016/S0167-9260(01)00020-7 |
0.463 |
|
| 2001 |
Shelar RS, Sapatnekar SS. Recursive bipartitioning of BDDs for performance driven synthesis of pass transistor logic circuits Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 449-452. |
0.791 |
|
| 2000 |
Zhao M, Sapatnekar SS. Timing-driven partitioning and timing optimization of mixed static-domino implementations Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 19: 1322-1336. DOI: 10.1109/43.892856 |
0.36 |
|
| 2000 |
Kasamsetty K, Ketkar M, Sapatnekar SS. A new class of convex functions for delay modeling and its application to the transistor sizing problem Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 19: 779-788. DOI: 10.1109/43.851993 |
0.721 |
|
| 2000 |
Hu J, Sapatnekar SS. Algorithms for non-hanan-based optimization for VLSI interconnect under a higher-order AWE model Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 19: 446-458. DOI: 10.1109/43.838994 |
0.486 |
|
| 2000 |
Sapatnekar SS, Chuang W. Power-Delay optimizations in gate sizing Acm Transactions On Design Automation of Electronic Systems. 5: 98-114. |
0.402 |
|
| 2000 |
Zhao M, Sapatnekar SS. Timingdriven partitioning and timing optimization of mixed staticdomino implementations Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 19: 13221336. |
0.375 |
|
| 2000 |
Zhao M, Sapatnekar SS. Dual-monotonic domino gate mapping and optimal output phase assignment of domino logic Proceedings - Ieee International Symposium On Circuits and Systems. 2. |
0.306 |
|
| 2000 |
Hu J, Sapatnekar SS. Timing-constrained algorithm for simultaneous global routing of multiple nets Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 99-103. |
0.336 |
|
| 1999 |
Maheshwari N, Sapatnekar SS. Optimizing large multiphase level-clocked circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 18: 1249-1264. DOI: 10.1109/43.784118 |
0.353 |
|
| 1999 |
Maheshwari N, Sapatnekar SS. Retiming control logic Integration, the Vlsi Journal. 28: 33-53. DOI: 10.1016/S0167-9260(99)00010-3 |
0.307 |
|
| 1998 |
Maheshwari N, Sapatnekar SS. Efficient minarea retiming of large level-clocked circuits Proceedings -Design, Automation and Test in Europe, Date. 840-845. DOI: 10.1109/DATE.1998.655956 |
0.368 |
|
| 1998 |
Maheshwari N, Sapatnekar S. Efficient retiming of large circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 6: 74-83. DOI: 10.1109/92.661250 |
0.523 |
|
| 1998 |
Sathyamurthy H, Sapatnekar SS, Fishburn JP. SpeEding up Pipelined Circuits through a Combination of Gate Sizing and Clock Skew Optimization Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 17: 173-182. DOI: 10.1109/43.681267 |
0.416 |
|
| 1998 |
Zhao M, Sapatnekar SS. Timing optimization of mixed static and domino logic Proceedings - Ieee International Symposium On Circuits and Systems. 6: 266-269. |
0.301 |
|
| 1998 |
Zhao M, Sapatnekar SS. Technology mapping for domino logic Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 248-251. |
0.355 |
|
| 1998 |
Jiang Y, Sapatnekar SS, Bamji C. Fast global gate collapsing technique for high performance designs using static CMOS and pass transistor logic Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 276-281. |
0.386 |
|
| 1997 |
Pilli S, Sapatnekar SS. Power estimation considering statistical IC parametric variations Proceedings - Ieee International Symposium On Circuits and Systems. 3: 1524-1527. |
0.359 |
|
| 1997 |
Maheshwari N, Sapatnekar SS. Improved algorithm for minimum-area retiming Proceedings - Design Automation Conference. 2-7. |
0.324 |
|
| 1996 |
Sapatnekar SS, Deokar RB. Utilizing the retiming-skew equivalence in a practical algorithm for retiming large circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 15: 1237-1248. DOI: 10.1109/43.541443 |
0.305 |
|
| 1996 |
Sancheti PK, Sapatnekar SS. Optimal design of macrocells for low power and high speed Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 15: 1160-1166. DOI: 10.1109/43.536722 |
0.363 |
|
| 1996 |
Sapatnekar SS. Wire sizing as a convex optimization problem: exploring the area-delay tradeoff Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 15: 1001-1011. DOI: 10.1109/43.511579 |
0.311 |
|
| 1996 |
Sapatnekar SS. Efficient calculation of all-pairs input-to-output delays in synchronous sequential circuits Proceedings - Ieee International Symposium On Circuits and Systems. 4: 520-523. |
0.402 |
|
| 1996 |
Shah JC, Sapatnekar SS. Wiresizing with buffer placement and sizing for power-delay tradeoffs Proceedings of the Ieee International Conference On Vlsi Design. 346-351. |
0.324 |
|
| 1996 |
Maheshwari N, Sapatnekar SS. Practical algorithm for retiming level-clocked circuits Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 440-445. |
0.371 |
|
| 1995 |
Sapatnekar SS, Chuang W. Power vs. delay in gate sizing: Conflicting objectives? Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 463-466. |
0.38 |
|
| 1995 |
Maheshwari N, Sapatnekar SS. Gate size optimization for row-based layouts Midwest Symposium On Circuits and Systems. 2: 777-780. |
0.38 |
|
| 1995 |
Sancheti PK, Sapatnekar SS. Layout optimization using arbitrarily high degree posynomial models Proceedings - Ieee International Symposium On Circuits and Systems. 1: 53-56. |
0.36 |
|
| 1994 |
Sapatnekar SS. RC interconnect optimization under the Elmore delay model Proceedings - Design Automation Conference. 387-391. |
0.302 |
|
| 1994 |
Sancheti PK, Sapatnekar SS. Interconnect design using convex optimization Proceedings of the Custom Integrated Circuits Conference. 549-552. |
0.302 |
|
| 1994 |
Deokar RB, Sapatnekar SS. Graph-theoretic approach to clock skew optimization Proceedings - Ieee International Symposium On Circuits and Systems. 1: 407-410. |
0.302 |
|
| 1990 |
Sapatnekar SS, Rao VB. iDEAS: A delay estimator and transistor sizing tool for CMOS circuits Proceedings of the Custom Integrated Circuits Conference. |
0.417 |
|
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