| Year |
Citation |
Score |
| 2004 |
Niggemeyer D, Rudnick EM. Automatic generation of diagnostic memory tests based on fault decomposition and output tracing Ieee Transactions On Computers. 53: 1134-1146. DOI: 10.1109/TC.2004.54 |
0.602 |
|
| 2003 |
Niggemeyer D, Rudnick EM. A Data Acquisition Methodology for on-Chip Repair of Embedded Memories Acm Transactions On Design Automation of Electronic Systems. 8: 560-576. DOI: 10.1145/944027.944037 |
0.524 |
|
| 2002 |
Yu X, Fin A, Fummi F, Rudnick EM. A genetic testing framework for digital integrated circuits Proceedings of the International Conference On Tools With Artificial Intelligence. 521-526. |
0.492 |
|
| 2002 |
Abramovici M, Yu X, Rudnick EM. Low-cost sequential ATPG with clock-control DFT Proceedings - Design Automation Conference. 243-248. |
0.341 |
|
| 2001 |
Hartanto I, Venkataraman S, Fuchs WK, Rudnick EM, Patel JH, Chakravarty S. Diagnostic simulation of stuck-at faults in sequential circuits using compact lists Acm Transactions On Design Automation of Electronic Systems. 6: 471-489. DOI: 10.1145/502175.502177 |
0.581 |
|
| 2001 |
Fummi F, Boschini M, Yu X, Rudnick EM. Sequential circuit test generation using a symbolic/genetic hybrid approach Journal of Electronic Testing: Theory and Applications (Jetta). 17: 321-330. DOI: 10.1023/A:1012275631257 |
0.585 |
|
| 2001 |
Niggemeyer D, Rudnick EM. Automatic generation of diagnostic March tests Proceedings of the Ieee Vlsi Test Symposium. 299-304. |
0.627 |
|
| 2001 |
Shin J, Yu X, Rudnick EM, Abramovici M. At-speed logic BIST using a frozen clock testing strategy Ieee International Test Conference (Tc). 64-71. |
0.533 |
|
| 2000 |
Rudnick EM, Abramovici M. Compact test generation using a frozen clock testing strategy Journal of Information Science and Engineering. 16: 703-717. DOI: 10.6688/Jise.2000.16.5.3 |
0.617 |
|
| 2000 |
Hsiao MS, Rudnick EM, Patel JH. Dynamic state traversal for sequential circuit test generation Acm Transactions On Design Automation of Electronic Systems. 5: 548-565. DOI: 10.1145/348019.348288 |
0.572 |
|
| 2000 |
Bergfeld TJ, Niggemeyer D, Rudnick EM. Diagnostic testing of embedded memories using BIST Proceedings -Design, Automation and Test in Europe, Date. 305-309. DOI: 10.1109/DATE.2000.840288 |
0.453 |
|
| 2000 |
Hsiao MS, Rudnick EM, Patel JH. Peak power estimation of VLSI circuits: New peak power measures Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 8: 435-439. DOI: 10.1109/92.863624 |
0.332 |
|
| 2000 |
Wu J, Rudnick EM. Bridge fault diagnosis using stuck-at fault simulation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 19: 489-495. DOI: 10.1109/43.838998 |
0.543 |
|
| 1999 |
Wu J, Greenstein GS, Rudnick EM. A fault list reduction approach for efficient bridge fault diagnosis Proceedings -Design, Automation and Test in Europe, Date. 780-781. DOI: 10.1109/DATE.1999.761228 |
0.511 |
|
| 1999 |
Santoso Y, Merten M, Rudnick EM, Abramovici M. FreezeFrame: Compact test generation using a frozen clock strategy Proceedings -Design, Automation and Test in Europe, Date. 747-752. DOI: 10.1109/DATE.1999.761214 |
0.617 |
|
| 1999 |
Rudnick EM, Patel JH. Efficient techniques for dynamic test sequence compaction Ieee Transactions On Computers. 48: 323-330. DOI: 10.1109/12.754998 |
0.666 |
|
| 1999 |
Hsiao MS, Rudnick EM, Patel JH. Fast static compaction algorithms for sequential circuit test vectors Ieee Transactions On Computers. 48: 311-322. DOI: 10.1109/12.754997 |
0.645 |
|
| 1998 |
Rudnick EM, Vietti R, Ellis A, Corno F, Prinetto P, Reorda MS. Fast sequential circuit test generation using high-level and gate-level techniques Proceedings -Design, Automation and Test in Europe, Date. 570-576. DOI: 10.1109/DATE.1998.655915 |
0.599 |
|
| 1998 |
Hsiao MS, Rudnick EM, Patel JH. Application of genetically engineered finite-statemachine sequences to sequential circuit ATPG Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 17: 239-254. DOI: 10.1109/43.700722 |
0.579 |
|
| 1997 |
Rudnick EM, Patel JH, Greenstein GS, Niermann TM. A genetic algorithm framework for test generation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 16: 1034-1044. DOI: 10.1109/43.658571 |
0.623 |
|
| 1997 |
Graham CR, Rudnick EM, Patel JH. Dynamic fault grouping for PROOFS: a win for large sequential circuits Proceedings of the Ieee International Conference On Vlsi Design. 542-544. |
0.573 |
|
| 1997 |
Rudnick EM, Patel JH. Overcoming the serial logic simulation bottleneck in parallel fault simulation Proceedings of the Ieee International Conference On Vlsi Design. 495-501. |
0.592 |
|
| 1997 |
Krishnaswamy D, Hsiao MS, Saxena V, Rudnick EM, Patel JH, Banerjee P. Parallel genetic algorithms for simulation-based sequential circuit test generation Proceedings of the Ieee International Conference On Vlsi Design. 475-481. |
0.499 |
|
| 1996 |
Cha H, Rudnick EM, Patel JH, Iyer RK, Choi GS. A gate-level simulation environment for alpha-particle-induced transient faults Ieee Transactions On Computers. 45: 1248-1256. DOI: 10.1109/12.544481 |
0.541 |
|
| 1995 |
Rudnick EM, Chickermane V, Banerjee P, Patel JH. Sequential Circuit Testability Enhancement Using a Nonscan Approach Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 3: 333-338. DOI: 10.1109/92.386233 |
0.628 |
|
| 1994 |
Rudnick EM, Patel JH, Chickermane V. An Observability Enhancement Approach for Improved Testability and At-Speed Test Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 13: 1051-1056. DOI: 10.1109/43.298041 |
0.643 |
|
| 1992 |
Rudnick EM, Fuchs WK, Patel JH. Diagnostic Fault Simulation of Sequential Circuits Proceedings - International Test Conference. 1992: 178-186. DOI: 10.1109/TEST.1992.527818 |
0.583 |
|
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