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Daniel Sorin - Publications

Affiliations: 
Computer Science Duke University, Durham, NC 
Area:
Computer Science
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39 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2016 Martin M, Sorin D. Top Picks from the 2015 Computer Architecture Conferences Ieee Micro. 36: 6-9. DOI: 10.1109/Mm.2016.47  0.347
2015 Jacobvitz AN, Hilton AD, Sorin DJ. Multi-program benchmark definition Ispass 2015 - Ieee International Symposium On Performance Analysis of Systems and Software. 72-82. DOI: 10.1109/ISPASS.2015.7095786  0.73
2013 Hechtman BA, Sorin DJ. Exploring memory consistency for massively-threaded throughput-oriented processors Proceedings - International Symposium On Computer Architecture. 201-212. DOI: 10.1145/2485922.2485940  0.764
2013 Hechtman BA, Sorin DJ. Evaluating cache coherent shared virtual memory for heterogeneous multicore chips Ispass 2013 - Ieee International Symposium On Performance Analysis of Systems and Software. 118-119. DOI: 10.1109/ISPASS.2013.6557152  0.762
2013 Jacobvitz AN, Calderbank R, Sorin DJ. Coset coding to extend the lifetime of memory Proceedings - International Symposium On High-Performance Computer Architecture. 222-233. DOI: 10.1109/HPCA.2013.6522321  0.766
2012 Jacobvitz AN, Calderbank R, Sorin DJ. Writing cosets of a convolutional code to increase the Lifetime of Flash memory 2012 50th Annual Allerton Conference On Communication, Control, and Computing, Allerton 2012. 308-318. DOI: 10.1109/Allerton.2012.6483234  0.77
2011 Sorin DJ, Hill MD, Wood DA. A primer on memory consistency and cache coherence Synthesis Lectures On Computer Architecture. 16: 1-212. DOI: 10.2200/S00346ED1V01Y201104CAC016  0.359
2011 Eibl PJ, Meixner A, Sorin DJ. An FPGA-based experimental evaluation of microprocessor core error detection with Argus-2 Performance Evaluation Review. 39: 121-122. DOI: 10.1145/2007116.2007131  0.603
2011 Romanescu B, Lebeck A, Sorin DJ. Address translation aware memory consistency Ieee Micro. 31: 109-118. DOI: 10.1109/Mm.2010.99  0.807
2011 Gizopoulos D, Psarakis M, Adve SV, Ramachandran P, Hari SKS, Sorin D, Meixner A, Biswas A, Vera X. Architectures for online error detection and recovery in multicore processors Proceedings -Design, Automation and Test in Europe, Date. 533-538.  0.33
2010 Romanescu BF, Lebeck AR, Sorin DJ. Specifying and dynamically verifying address translation-aware memory consistency International Conference On Architectural Support For Programming Languages and Operating Systems - Asplos. 323-334. DOI: 10.1145/1736020.1736057  0.808
2010 Zhang M, Lebeck A, Sorin D. Fractal consistency: Architecting the memory system to facilitate verification Ieee Computer Architecture Letters. 9: 61-64. DOI: 10.1109/L-Ca.2010.18  0.336
2010 Romanescu BF, Lebeck AR, Sorin DJ, Bracy A. Unified Instruction/Translation/Data (UNITD) coherence: One protocol to rule them all Proceedings - International Symposium On High-Performance Computer Architecture.  0.769
2009 Lungu A, Bose P, Buyuktosunoglu A, Sorin DJ. Dynamic power gating with quality guarantees Proceedings of the International Symposium On Low Power Electronics and Design. 377-382. DOI: 10.1145/1594233.1594331  0.471
2009 Lungu A, Bose P, Sorin DJ, German S, Janssen G. Multicore power management: Ensuring robustness via early-stage formal verification 2009 7th Ieee-Acm International Conference On Formal Methods and Models For Co-Design, Memocode '09. 78-87. DOI: 10.1109/MEMCOD.2009.5185383  0.521
2009 Zhang M, Lungu A, Sorin DJ. Analyzing formal verification and testing efforts of different fault tolerance mechanisms Proceedings - Ieee International Symposium On Defect and Fault Tolerance in Vlsi Systems. 277-285. DOI: 10.1109/DFT.2009.23  0.576
2008 Romanescu BF, Sorin DJ. Core cannibalization architecture: Improving lifetime chip performance for multicore processors in the presence of hard faults Parallel Architectures and Compilation Techniques - Conference Proceedings, Pact. 43-51. DOI: 10.1145/1454115.1454124  0.794
2008 Romanescu BF, Bauer ME, Ozev S, Sorin DJ. Reducing the impact of intra-core process variability with criticality-based resource allocation and prefetching Conference On Computing Frontiers - Proceedings of the 2008 Conference On Computing Frontiers, Cf'08. 129-138. DOI: 10.1145/1366230.1366257  0.757
2008 Bower FA, Sorin DJ, Cox LP. The impact of dynamically heterogeneous multicore processors on thread scheduling Ieee Micro. 28: 17-25. DOI: 10.1109/Mm.2008.46  0.781
2008 Meixner A, Bauer ME, Sorin DJ. Argus: Low-cost, comprehensive error detection in simple cores Ieee Micro. 28: 52-59. DOI: 10.1109/Mm.2008.3  0.573
2008 Meixner A, Sorin DJ. Detouring: Translating software to circumvent hard faults in simple cores Proceedings of the International Conference On Dependable Systems and Networks. 80-89. DOI: 10.1109/DSN.2008.4630073  0.613
2007 Meixner A, Sorin DJ. Unified microprocessor core storage 2007 Computing Frontiers, Conference Proceedings. 23-34. DOI: 10.1145/1242531.1242538  0.536
2007 Meixner A, Sorin DJ. Error detection using dynamic dataflow verification Parallel Architectures and Compilation Techniques - Conference Proceedings, Pact. 104-115. DOI: 10.1109/PACT.2007.26  0.58
2007 Lungu A, Sorin DJ. Verification-aware microprocessor design Parallel Architectures and Compilation Techniques - Conference Proceedings, Pact. 83-93. DOI: 10.1109/PACT.2007.17  0.535
2007 Romanescu BF, Bauer ME, Sorin DJ, Ozev S. Reducing the impact of process variability with prefetching and criticality-based resource allocation Parallel Architectures and Compilation Techniques - Conference Proceedings, Pact. 424. DOI: 10.1109/PACT.2007.16  0.739
2007 Meixner A, Sorin DJ. Error detection via online checking of cache coherence with token coherence signatures Proceedings - International Symposium On High-Performance Computer Architecture. 145-156. DOI: 10.1109/HPCA.2007.346193  0.635
2007 Yilmaz M, Meixner A, Ozev S, Sorin DJ. Lazy error detection for microprocessor functional units Proceedings - Ieee International Symposium On Defect and Fault Tolerance in Vlsi Systems. 361-369. DOI: 10.1109/DFT.2007.16  0.504
2006 Bower FA, Hower D, Yilmaz M, Sorin DJ, Ozev S. Applying architectural vulnerability analysis to hard faults in the microprocessor Performance Evaluation Review. 34: 375-376. DOI: 10.1145/1140103.1140327  0.794
2006 Meixner A, Sorin DJ. Dynamic verification of memory consistency in cache-coherent multithreaded computer architectures Proceedings of the International Conference On Dependable Systems and Networks. 2006: 73-82. DOI: 10.1109/Tdsc.2007.70243  0.64
2005 Bower FA, Ozev S, Sorin DJ. Autonomic microprocessor execution via self-repairing arrays Ieee Transactions On Dependable and Secure Computing. 2: 297-310. DOI: 10.1109/Tdsc.2005.44  0.793
2005 Bower FA, Sorin DJ, Ozev S. A mechanism for online diagnosis of hard faults in microprocessors Proceedings of the Annual International Symposium On Microarchitecture, Micro. 197-208. DOI: 10.1109/MICRO.2005.8  0.788
2005 Meixner A, Sorin DJ. Dynamic verification of sequential consistency Proceedings - International Symposium On Computer Architecture. 482-493. DOI: 10.1109/ISCA.2005.25  0.637
2004 Bower FA, Shealy PG, Ozev S, Sorin DJ. Tolerating hard faults in microprocessor array structures Proceedings of the International Conference On Dependable Systems and Networks. 51-60.  0.773
2003 Sorin DJ, Lemon JL, Eager DL, Vernon MK. Analytic evaluation of shared-memory architectures Ieee Transactions On Parallel and Distributed Systems. 14: 166-180. DOI: 10.1109/Tpds.2003.1178880  0.336
2003 Sorin DJ, Hill MD, Wood DA. Dynamic Verification of End-to-End Multiprocessor Invariants Proceedings of the International Conference On Dependable Systems and Networks. 281-290. DOI: 10.1109/DSN.2003.1209938  0.39
2002 Sorin DJ, Plakal M, Condon AE, Hill MD, Martin MMK, Wood DA. Specifying and verifying a broadcast and a multicast snooping cache coherence protocol Ieee Transactions On Parallel and Distributed Systems. 13: 556-578. DOI: 10.1109/Tpds.2002.1011412  0.3
2002 Sorin DJ, Martin MMK, Hill MD, Wood DA. SafetyNet: Improving the availability of shared memory multiprocessors with global checkpoint/recovery Conference Proceedings - Annual International Symposium On Computer Architecture, Isca. 123-134.  0.31
2000 Martin MMK, Sorin DJ, Ailamaki A, Alameldeen AR, Dickson RM, Mauer CJ, Moore KE, Plakal M, Hill MD, Wood DA. Timestamp snooping: An approach for extending SMPs Sigplan Notices (Acm Special Interest Group On Programming Languages). 35: 25-36.  0.335
1998 Plakal M, Sorin DJ, Condon AE, Hill MD. Lamport clocks: verifying a directory cache-coherence protocol Annual Acm Symposium On Parallel Algorithms and Architectures. 67-76.  0.356
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