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Alper Buyuktosunoglu, Ph.D. - Publications

Affiliations: 
2003 University of Rochester, Rochester, NY 
Area:
Electronics and Electrical Engineering, Computer Science
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47 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Webel T, Lobo PM, Strach T, Parashurama PB, Purushotham S, Bertran R, Buyuktosunoglu A. Proactive power management in IBM z15 Journal of Reproduction and Development. 64. DOI: 10.1147/Jrd.2020.3008143  0.32
2020 Ortega C, Alvarez L, Casas M, Bertran R, Buyuktosunoglu A, Eichenberger AE, Bose P, Moreto M. Intelligent Adaptation Of Hardware Knobs For Improving Performance and Power Consumption Ieee Transactions On Computers. 1-1. DOI: 10.1109/Tc.2020.2980230  0.457
2019 Leng J, Buyuktosunoglu A, Bertran R, Bose P, Reddi VJ. Asymmetric Resilience for Accelerator-Rich Systems Ieee Computer Architecture Letters. 18: 83-86. DOI: 10.1109/Lca.2019.2917898  0.412
2019 Berry C, Wolpert D, Vezrytzis C, Rizzolo R, Carey S, Maroz Y, Shi H, Chidambarrao D, Jacobi C, Saporito A, Strach T, Buyuktosunoglu A, Lobo P, Chuang P, Owczarczyk P, et al. IBM z14: Processor Characterization and Power Management for High-Reliability Mainframe Systems Ieee Journal of Solid-State Circuits. 54: 121-132. DOI: 10.1109/Jssc.2018.2873582  0.455
2018 Fluhr EJ, Rao RM, Smith H, Buyuktosunoglu A, Bertran R. IBM POWER9 circuit design and energy optimization for 14-nm technology Journal of Reproduction and Development. 62: 4. DOI: 10.1147/Jrd.2018.2846158  0.436
2018 Berry CJ, Warnock JD, Badar J, Bair DG, Behnen E, Bell B, Buyuktosunoglu A, Cavitt C, Chuang P, Geva O, Hamid D, Isakson J, Lobo P, Malgioglio F, Mayer G, et al. IBM z14 design methodology enhancements in the 14-nm technology node Journal of Reproduction and Development. 62: 1-1. DOI: 10.1147/Jrd.2018.2800218  0.414
2017 Ziegler MM, Bertran R, Buyuktosunoglu A, Bose P. Machine learning techniques for taming the complexity of modern hardware design Journal of Reproduction and Development. 61: 13. DOI: 10.1147/Jrd.2017.2721699  0.379
2017 Sasaki H, Buyuktosunoglu A, Vega A, Bose P. Mitigating Power Contention: A Scheduling Based Approach Ieee Computer Architecture Letters. 16: 60-63. DOI: 10.1109/Lca.2016.2572080  0.432
2015 Webel T, Lobo PM, Bertran R, Salem GM, Allen-Ware M, Rizzolo R, Carey SM, Strach T, Buyuktosunoglu A, Lefurgy C, Bose P, Nigaglioni R, Slegel T, Floyd MS, Curran BW. Robust power management in the IBM z13 Ibm Journal of Research and Development. 59. DOI: 10.1147/Jrd.2015.2446872  0.441
2015 Wang L, Vega AJ, Buyuktosunoglu A, Bose P, Skadron K. Power-efficient embedded processing with resilience and real-time constraints Proceedings of the International Symposium On Low Power Electronics and Design. 2015: 231-236. DOI: 10.1109/ISLPED.2015.7273519  0.327
2014 Pugsley SH, Jestes J, Balasubramonian R, Srinivasan V, Buyuktosunoglu A, Davis A, Li F. Comparing implementations of near-data computing with in-memory mapreduce workloads Ieee Micro. 34: 44-52. DOI: 10.1109/Mm.2014.54  0.316
2014 Vega A, Buyuktosunoglu A, Bose P. Special series on harsh chips Ieee Micro. 34: 6-7. DOI: 10.1109/Mm.2014.102  0.307
2013 Bertran R, Sugawara Y, Jacobson HM, Buyuktosunoglu A, Bose P. Application-level power and performance characterization and optimization on IBM Blue Gene/Q systems Journal of Reproduction and Development. 57: 38-53. DOI: 10.1147/Jrd.2012.2227580  0.439
2013 Morari A, Boneti C, Cazorla FJ, Gioiosa R, Cher CY, Buyuktosunoglu A, Bose P, Valero M. SMT malleability in IBM POWER5 and POWER6 processors Ieee Transactions On Computers. 62: 813-826. DOI: 10.1109/Tc.2012.34  0.423
2013 Sarikaya R, Isci C, Buyuktosunoglu A. Runtime application behavior prediction using a statistical metric model Ieee Transactions On Computers. 62: 575-588. DOI: 10.1109/Tc.2012.25  0.365
2013 Tembey P, Vega A, Buyuktosunoglu A, Da Silva D, Bose P. SMT switch: Software mechanisms for power shifting Ieee Computer Architecture Letters. 12: 67-70. DOI: 10.1109/L-Ca.2012.26  0.411
2012 Jiménez V, Gioiosa R, Cazorla FJ, Buyuktosunoglu A, Bose P, O'Connell FP. Making data prefetch smarter: Adaptive prefetching on power 7 Parallel Architectures and Compilation Techniques - Conference Proceedings, Pact. 137-146. DOI: 10.1145/2370816.2370837  0.392
2012 Luque C, Moreto M, Cazorla FJ, Gioiosa R, Buyuktosunoglu A, Valero M. CPU accounting for multicore processors Ieee Transactions On Computers. 61: 251-264. DOI: 10.1109/Tc.2011.152  0.32
2012 Wenisch TF, Buyuktosunoglu A. Energy-aware computing Ieee Micro. 32: 6-8. DOI: 10.1109/Mm.2012.78  0.328
2012 Huang W, Lefurgy C, Kuk W, Buyuktosunoglu A, Floyd M, Rajamani K, Allen-Ware M, Brock B. Accurate fine-grained processor power proxies Proceedings - 2012 Ieee/Acm 45th International Symposium On Microarchitecture, Micro 2012. 224-234. DOI: 10.1109/MICRO.2012.29  0.357
2012 Bertran R, Buyuktosunoglu A, Gupta MS, Gonzalez M, Bose P. Systematic energy characterization of CMP/SMT processor systems via automated micro-benchmarks Proceedings - 2012 Ieee/Acm 45th International Symposium On Microarchitecture, Micro 2012. 199-211. DOI: 10.1109/MICRO.2012.27  0.333
2011 Floyd M, Ware M, Rajamani K, Gloekler T, Brock B, Bose P, Buyuktosunoglu A, Rubio JC, Schubert B, Spruth B, Tierno JA, Pesantez L. Adaptive energy-management features of the IBM POWER7 chip Ibm Journal of Research and Development. 55. DOI: 10.1147/Jrd.2011.2114250  0.469
2011 Jiménez V, Cazorla FJ, Gioiosa R, Kursun E, Isci C, Buyuktosunoglu A, Bose P, Valero M. Energy-aware accounting and billing in large-scale computing facilities Ieee Micro. 31: 60-71. DOI: 10.1109/Mm.2011.35  0.399
2011 Floyd M, Allen-Ware M, Rajamani K, Brock B, Lefurgy C, Drake AJ, Pesantez L, Gloekler T, Tierno JA, Bose P, Buyuktosunoglu A. Introducing the adaptive energy management features of the power7 chip Ieee Micro. 31: 60-74. DOI: 10.1109/Mm.2011.29  0.454
2011 Jiménez V, Cazorla FJ, Gioiosa R, Valero M, Boneti C, Kursun E, Cher CY, Isci C, Buyuktosunoglu A, Bose P. Characterizing power and temperature behavior of POWER6-based system Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 1: 228-241. DOI: 10.1109/Jetcas.2011.2169630  0.4
2010 Kȩdzierski K, Cazorla FJ, Gioiosa R, Buyuktosunoglu A, Valero M. Power and performance aware reconfigurable cache for CMPs Acm International Conference Proceeding Series. DOI: 10.1145/1882453.1882455  0.407
2010 Jiménez V, Cazorla FJ, Gioiosa R, Valero M, Boneti C, Kursun E, Cher CY, Isci C, Buyuktosunoglu A, Bose P. Power and thermal characterization of POWER6 system Parallel Architectures and Compilation Techniques - Conference Proceedings, Pact. 7-18. DOI: 10.1145/1854273.1854281  0.31
2010 Jiménez V, Gioiosa R, Kursun E, Cazorla FJ, Cher CY, Buyuktosunoglu A, Bose P, Valero M. Trends and techniques for energy efficient architectures Proceedings of the 2010 18th Ieee/Ifip International Conference On Vlsi and System-On-Chip, Vlsi-Soc 2010. 276-279. DOI: 10.1109/VLSISOC.2010.5642673  0.353
2009 Lungu A, Bose P, Buyuktosunoglu A, Sorin DJ. Dynamic power gating with quality guarantees Proceedings of the International Symposium On Low Power Electronics and Design. 377-382. DOI: 10.1145/1594233.1594331  0.338
2008 Boneti C, Cazorla FJ, Gioiosa R, Buyuktosunoglu A, Cher CY, Valero M. Software-controlled priority characterization of POWERS processor Proceedings - International Symposium On Computer Architecture. 415-426. DOI: 10.1109/ISCA.2008.8  0.304
2008 Bergamaschi R, Han G, Buyuktosunoglu A, Patel H, Nair I, Dittmann G, Janssen G, Dhanwada N, Hu Z, Bose P, Darringer J. Exploring power management in multi-core systems Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 708-713. DOI: 10.1109/ASPDAC.2008.4484043  0.323
2007 Sharkey J, Buyuktosunoglu A, Bose P. Evaluating design tradeoffs in on-chip power management for CMPs Proceedings of the International Symposium On Low Power Electronics and Design. 44-49. DOI: 10.1145/1283780.1283791  0.302
2006 Isci C, Buyuktosunoglu A, Cher CY, Bose P, Martonosi M. An analysis of efficient multi-core global power management policies: Maximizing performance for a given power budget Proceedings of the Annual International Symposium On Microarchitecture, Micro. 347-358. DOI: 10.1109/MICRO.2006.8  0.324
2005 Isci C, Buyuktosunoglu A, Martonosi M. Long-term workload phases: Duration predictions and applications to DVFS Ieee Micro. 25: 39-51. DOI: 10.1109/Mm.2005.93  0.396
2005 Jacobson H, Bose P, Hu Z, Buyuktosunoglu A, Zyuban V, Eickemeyer R, Eisen L, Griswell J, Logan D, Sinharoy B, Tendier J. Stretching the limits of clock-gating efficiency in server-class processors Proceedings - International Symposium On High-Performance Computer Architecture. 238-242. DOI: 10.1109/HPCA.2005.33  0.319
2005 Zhu Y, Albonesi DH, Buyuktosunoglu A. A high performance, energy efficient GALS processor microarchitecture with reduced implementation complexity Ispass 2005 - Ieee International Symposium On Performance Analysis of Systems and Software. 2005: 42-53.  0.645
2004 Balasubramonian R, Srinivasan V, Dwarkadas S, Buyuktosunoglu A. Hot-and-cold: Using criticality in the design of energy-efficient caches Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 3164: 180-195.  0.382
2003 Balasubramonian R, Albonesi DH, Buyuktosunoglu A, Dwarkadas S. A dynamically tunable memory hierarchy Ieee Transactions On Computers. 52: 1243-1258. DOI: 10.1109/Tc.2003.1234523  0.686
2003 Albonesi DH, Balasubramonian R, Dropsho SG, Dwarkadas S, Friedman EG, Huang MC, Kursun V, Magklis G, Scott ML, Semeraro G, Bose P, Buyuktosunoglu A, Cook PW, Schuster SE. Dynamically Tuning Processor Resources with Adaptive Processing Computer. 36: 49-50+4. DOI: 10.1109/Mc.2003.1250883  0.497
2003 Buyuktosunoglu A, Karkhanis T, Albonesi DH, Bose P. Energy efficient co-adaptive instruction fetch and issue Conference Proceedings - Annual International Symposium On Computer Architecture, Isca. 147-156.  0.653
2002 Dropsho S, Buyuktosunoglu A, Balasubramonian R, Albonesi DH, Dwarkadas S, Semeraro G, Magklis G, Scottt ML. Integrating adaptive on-chip storage structures for reduced dynamic power Parallel Architectures and Compilation Techniques - Conference Proceedings, Pact. 2002: 141-152. DOI: 10.1109/PACT.2002.1106013  0.675
2002 Buyuktosunoglu A, El-Moursy A, Albonesi DH. An oldest-first selection logic implementation for non-compacting issue queues Proceedings of the Annual Ieee International Asic Conference and Exhibit. 2002: 31-35. DOI: 10.1109/ASIC.2002.1158026  0.656
2002 Buyuktosunoglu A, Albonesi DH, Bose P, Cook PW, Schuster SE. Tradeoffs in power-efficient issue queue design Proceedings of the International Symposium On Low Power Electronics and Design, Digest of Technical Papers. 184-189.  0.632
2001 Buyuktosunoglu A, Schuster S, Brooks D, Bose P, Cook P, Albonesi D. An adaptive issue queue for reduced power at high performance Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 2008: 25-39.  0.459
2001 Buyuktosunoglu A, Albonesi D, Schuster S, Brooks D, Bose P, Cook P. A circuit level implementation of an adaptive issue queue for power-aware microprocessors Proceedings of the Ieee Great Lakes Symposium On Vlsi. 73-78.  0.456
2000 Brooks DM, Bose P, Schuster SE, Jacobson H, Kudva PN, Buyuktosunoglu A, Wellman J, Zyuban V, Gupta M, Cook PW. Power-aware microarchitecture: design and modeling challenges for next-generation microprocessors Ieee Micro. 20: 26-44. DOI: 10.1109/40.888701  0.467
2000 Brooks DM, Bose P, Schuster SE, Jacobson H, Kudva PN, Buyuktosunoglu A, Wellman JD, Zyuban V, Gupta M, Cook PW. Power-aware microarchitecture: Design and modeling challenges for next-generation microprocessors Ieee Micro. 20: 26-43.  0.321
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