Zhiyi Yu, Ph.D.
Affiliations: | 2007 | University of California, Davis, Davis, CA |
Area:
Electronics and Electrical EngineeringGoogle:
"Zhiyi Yu"Parents
Sign in to add mentor| Bevan M. Baas | grad student | 2007 | UC Davis | |
| (High performance and energy efficient multi-core systems for DSP applications.) | ||||
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Publications
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| Zeng J, Zhang Z, Chen R, et al. (2020) DM-IMCA: A Dual-mode In-Memory Computing Architecture for General Purpose Processing Ieice Electronics Express. 17: 20200005-20200005 |
| Xiao S, Guo Y, Liao W, et al. (2020) NeuronLink: An Efficient Chip-to-Chip Interconnect for Large-Scale Neural Network Accelerators Ieee Transactions On Very Large Scale Integration Systems. 28: 1966-1978 |
| Chen X, Yu Z. (2018) A Flexible and Energy-Efficient Convolutional Neural Network Acceleration With Dedicated ISA and Accelerator Ieee Transactions On Very Large Scale Integration Systems. 26: 1408-1412 |
| Zeng J, Wu C, Zhang Z, et al. (2017) A multi-core-based heterogeneous parallel turbo decoder Ieice Electronics Express. 14: 20170768-20170768 |
| Shi W, Li X, Yu Z, et al. (2017) An FPGA-Based Hardware Accelerator for Traffic Sign Detection Ieee Transactions On Very Large Scale Integration Systems. 25: 1362-1372 |
| Manoj PDS, Lin J, Zhu S, et al. (2017) A Scalable Network-on-Chip Microprocessor With 2.5D Integrated Memory and Accelerator Ieee Transactions On Circuits and Systems I-Regular Papers. 64: 1432-1443 |
| Guo Y, Wu Y, Guo D, et al. (2015) Non-binary Digital calibration for split-capacitor DAC in SAR ADC Ieice Electronics Express. 12: 20150001-20150001 |
| Yu J, Zhou W, Yang Y, et al. (2015) Many-Core Processors Granularity Evaluation by Considering Performance, Yield, and Lifetime Reliability Ieee Transactions On Very Large Scale Integration Systems. 23: 2043-2053 |
| Zeng X, Li Y, Zhang Y, et al. (2015) Design and Analysis of Highly Energy/Area-Efficient Multiported Register Files With Read Word-Line Sharing Strategy in 65-nm CMOS Process Ieee Transactions On Very Large Scale Integration Systems. 23: 1365-1369 |
| Han J, Li Y, Yu Z, et al. (2015) A 65 nm Cryptographic Processor for High Speed Pairing Computation Ieee Transactions On Very Large Scale Integration Systems. 23: 692-701 |