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Gael F. Close, Ph.D. - Publications

Affiliations: 
2008 Stanford University, Palo Alto, CA 
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13 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2013 Close GF, Frey U, Morrish J, Jordan R, Lewis SC, Maffitt T, Brightsky MJ, Hagleitner C, Lam CH, Eleftheriou E. A 256-mcell phase-change memory chip operating at 2+ bit/cell Ieee Transactions On Circuits and Systems I: Regular Papers. 60: 1521-1533. DOI: 10.1109/Tcsi.2012.2220459  0.302
2010 Chen X, Akinwande D, Lee KJ, Close GF, Yasuda S, Paul BC, Fujita S, Kong J, Wong HSP. Fully integrated graphene and carbon nanotube interconnects for gigahertz high-speed CMOS electronics Ieee Transactions On Electron Devices. 57: 3137-3143. DOI: 10.1109/Ted.2010.2069562  0.459
2009 Close GF, Yasuda S, Paul BC, Fujita S, Wong HSP. Measurement of subnanosecond delay through multiwall carbon-nanotube local interconnects in a CMOS integrated circuit Ieee Transactions On Electron Devices. 56: 43-49. DOI: 10.1109/Ted.2008.2008682  0.493
2009 Chen X, Lee KJ, Akinwande D, Close GF, Yasuda S, Paul B, Fujita S, Kong J, Wong HSP. High-speed graphene interconnects monolithically integrated with CMOS ring oscillators operating at 1.3GHz Technical Digest - International Electron Devices Meeting, Iedm. 23.6.1-23.6.4. DOI: 10.1109/IEDM.2009.5424293  0.337
2008 Close GF, Yasuda S, Paul B, Fujita S, Wong HS. A 1 GHz integrated circuit with carbon nanotube interconnects and silicon transistors. Nano Letters. 8: 706-9. PMID 18269256 DOI: 10.1021/Nl0730965  0.528
2008 Close GF, Philip Wong HS. Assembly and electrical characterization of multiwall carbon nanotube interconnects Ieee Transactions On Nanotechnology. 7: 596-600. DOI: 10.1109/Tnano.2008.927373  0.422
2008 Akinwande D, Yasuda S, Paul B, Fujita S, Close G, Wong H-P. Monolithic Integration of CMOS VLSI and Carbon Nanotubes for Hybrid Nanotechnology Applications Ieee Transactions On Nanotechnology. 7: 636-639. DOI: 10.1109/Tnano.2008.2003438  0.491
2008 Yasuda S, Akinwande D, Close GF, Philip Wong HS, Paul BC, Fujita S. Fault-tolerant circuit for carbon nanotube transistors with si-CMOS hybrid circuitry 2008 8th Ieee Conference On Nanotechnology, Ieee-Nano. 684-687. DOI: 10.1109/NANO.2008.207  0.425
2008 Close GF, Yasuda S, Paul B, Fujita S, Wong HSP. Sub-ns delay through multi-wall carbon nanotube local interconnects in a CMOS integrated circuit 2008 Ieee International Interconnect Technology Conference, Iitc. 234-236. DOI: 10.1109/IITC.2008.4546976  0.497
2007 Close GF, Wong HSP. Fabrication and characterization of carbon nanotube interconnects Technical Digest - International Electron Devices Meeting, Iedm. 203-206. DOI: 10.1109/IEDM.2007.4418902  0.467
2006 Akinwande D, Close GF, Philip Wong HS. Analysis of the frequency response of carbon nanotube transistors Ieee Transactions On Nanotechnology. 5: 599-604. DOI: 10.1109/Tnano.2006.880451  0.425
2006 Close GF, Wong HSP. Nanostructured materials for interconnects Advanced Metallization Conference (Amc). 2006: 3-13.  0.307
2006 Close GF, Wong HSP. Measurability issues in the radio-frequency characterization of carbon nanotubes 2006 6th Ieee Conference On Nanotechnology, Ieee-Nano 2006. 1: 266-269.  0.335
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