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Jafar Savoj, Ph.D. - Publications

Affiliations: 
2001 University of California, Los Angeles, Los Angeles, CA 
Area:
Analog, RF, mixed-signal integrated circuit design, dual-standard RF transceivers, phase-locked systems and frequency synthesizers, A/D and D/A converters, high-speed data communication circuits
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20 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2015 Frans Y, Carey D, Erett M, Amir-Aslanzadeh H, Fang WY, Turker D, Jose AP, Bekele A, Im J, Upadhyaya P, Wu ZD, Hsieh KCH, Savoj J, Chang K. A 0.5-16.3 Gb/s fully adaptive flexible-reach transceiver for FPGA in 20 nm CMOS Ieee Journal of Solid-State Circuits. 50: 1932-1944. DOI: 10.1109/Jssc.2015.2413849  0.547
2015 Upadhyaya P, Savoj J, An FT, Bekele A, Jose A, Xu B, Wu D, Furker D, Aslanzadeh H, Hedayati H, Im J, Lim SW, Chen S, Pham T, Frans Y, et al. A 0.5-to-32.75Gb/s flexible-reach wireline transceiver in 20nm CMOS Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 58: 56-57. DOI: 10.1109/ISSCC.2015.7062923  0.345
2015 Chang K, Savoj J, Upadhyaya P, Frans Y. Device aware high-speed transceiver design in planar and FinFet technologies Technical Digest - International Electron Devices Meeting, Iedm. 2015: 18.1.1-18.1.4. DOI: 10.1109/IEDM.2014.7047074  0.369
2014 Chien JC, Upadhyaya P, Jung H, Chen S, Fang W, Niknejad AM, Savoj J, Chang K. 2.8 A pulse-position-modulation phase-noise-reduction technique for a 2-to-16GHz injection-locked ring oscillator in 20nm CMOS Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 57: 52-53. DOI: 10.1109/ISSCC.2014.6757334  0.383
2014 Savoj J, Aslanzadeh H, Carey D, Erett M, Fang W, Frans Y, Hsieh K, Im J, Jose A, Turker D, Upadhyaya P, Wu D, Chang K. Wideband flexible-reach techniques for a 0.5-16.3Gb/s fully-adaptive transceiver in 20nm CMOS Proceedings of the Ieee 2014 Custom Integrated Circuits Conference, Cicc 2014. DOI: 10.1109/CICC.2014.6945980  0.362
2013 Savoj J, Hsieh KCH, An FT, Gong J, Im J, Jiang X, Jose AP, Kireev V, Lim SW, Roldan A, Turker DZ, Upadhyaya P, Wu D, Chang K. A low-power 0.5-6.6 Gb/s wireline transceiver embedded in low-cost 28 nm FPGAs Ieee Journal of Solid-State Circuits. 48: 2581-2594. DOI: 10.1109/Jssc.2013.2274824  0.417
2012 Savoj J, Hsieh K, An FT, Buckley M, Im J, Jiang X, Jose A, Kireev V, Lai KW, Pham H, Turker D, Wu D, Chang K. A low-power 6.6-Gb/s wireline transceiver for low-cost FPGAs in 28nm CMOS Proceedings - 2012 Ieee Asian Solid-State Circuits Conference, a-Sscc. 37-40. DOI: 10.1109/IPEC.2012.6522617  0.303
2008 Savoj J, Abbasfar A, Amirkhany A, Jeeradit M, Garlepp BW. A 12-GS/s phase-calibrated CMOS digital-to-analog converter for backplane communications Ieee Journal of Solid-State Circuits. 43: 1207-1215. DOI: 10.1109/Jssc.2008.920319  0.537
2008 Amirkhany A, Abbasfar A, Savoj J, Jeeradit M, Garlepp B, Kollipara RT, Stojanovic V, Horowitz M. A 24 Gb/s software programmable analog multi-tone transmitter Ieee Journal of Solid-State Circuits. 43: 999-1008. DOI: 10.1109/Jssc.2008.917520  0.32
2008 Amirkhany A, Abbasfar A, Savoj J, Horowitz MA. Time-variant characterization and compensation of wideband circuits Proceedings of the Custom Integrated Circuits Conference. 487-490. DOI: 10.1109/CICC.2007.4405778  0.469
2007 Amirkhany A, Abbasfar A, Savoj J, Jeeradit M, Garlepp B, Stojanovic V, Horowitz M. A 24Gb/s software programmable multi-channel transmitter Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 38-39. DOI: 10.1109/VLSIC.2007.4342757  0.376
2006 Savoj J, Kolagotla RK, Gharpurey R. Introduction to the special issue on the IEEE 2005 custom integrated circuits Conference Ieee Journal of Solid-State Circuits. 41: 1683-1684. DOI: 10.1109/Jssc.2008.925600  0.404
2005 Savoj J, Roo P. A 3.125-Gb/s sub-milliwatt CMOS signal detector circuit Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 2005: 198-201. DOI: 10.1109/VLSIC.2005.1469366  0.58
2005 Wang AZH, Natarajan S, Savoj J. Introduction to the special issue on the IEEE 2004 custom integrated circuits conference Ieee Journal of Solid-State Circuits. 40: 1775-1776. DOI: 10.1109/JSSC.2005.850276  0.383
2003 Savoj J, Razavi B. A 10-Gb/s CMOS clock and data recovery circuit with a half-rate binary phase/frequency detector Ieee Journal of Solid-State Circuits. 38: 13-21. DOI: 10.1109/Jssc.2002.806284  0.503
2002 Vadipour M, Savoj J. A low-power 20-Gb/s CMOS 2:1 multiplexer/driver European Solid-State Circuits Conference. 231-234.  0.544
2001 Savoj J, Razavi B. A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector Ieee Journal of Solid-State Circuits. 36: 761-768. DOI: 10.1109/4.918913  0.5
2001 Savoj J, Razavi B. Design of half-rate clock and data recovery circuits for optical communication systems Proceedings - Design Automation Conference. 121-126.  0.734
2001 Savoj J, Razavi B. A 10Gb/s CMOS clock and data recovery circuit with frequency detection Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 78-79+434.  0.668
2000 Savoj J, Razavi B. 10-Gb/s CMOS clock and data recovery circuit Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 136-139.  0.835
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