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Chen-Yong Cher, Ph.D. - Publications

Affiliations: 
2004 Purdue University, West Lafayette, IN, United States 
Area:
Electronics and Electrical Engineering
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18 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2018 Cheng E, Mirkhani S, Szafaryn LG, Cher C, Cho H, Skadron K, Stan MR, Lilja K, Abraham JA, Bose P, Mitra S. Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience) Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 1839-1852. DOI: 10.1109/Tcad.2017.2752705  0.371
2017 Cho H, Cheng E, Shepherd T, Cher C, Mitra S. System-Level Effects of Soft Errors in Uncore Components Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 36: 1497-1510. DOI: 10.1109/Tcad.2017.2651824  0.374
2015 Nair R, Antao SF, Bertolli C, Bose P, Brunheroto JR, Chen T, Cher CY, Costa CHA, Doi J, Evangelinos C, Fleischer BM, Fox TW, Gallo DS, Grinberg L, Gunnels JA, et al. Active memory cube: A processing-in-memory architecture for exascale systems Ibm Journal of Research and Development. 59. DOI: 10.1147/Jrd.2015.2409732  0.368
2013 Morari A, Boneti C, Cazorla FJ, Gioiosa R, Cher CY, Buyuktosunoglu A, Bose P, Valero M. SMT malleability in IBM POWER5 and POWER6 processors Ieee Transactions On Computers. 62: 813-826. DOI: 10.1109/Tc.2012.34  0.432
2011 Cher CY, Kursun E. Exploring the effects of on-chip thermal variation on high-performance multicore architectures Transactions On Architecture and Code Optimization. 8. DOI: 10.1145/1952998.1953000  0.37
2011 Jiménez V, Cazorla FJ, Gioiosa R, Valero M, Boneti C, Kursun E, Cher CY, Isci C, Buyuktosunoglu A, Bose P. Characterizing power and temperature behavior of POWER6-based system Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 1: 228-241. DOI: 10.1109/Jetcas.2011.2169630  0.395
2011 Ge R, Gioiosa R, Bellosa F, Boku T, Chen Y, Cher CY, Cesati M, De Supinski B, Feng X, Feng WC, Hsu CH, Isci C, Knauerhase R, Lefevre L, Lowenthal D, et al. High-performance, power-aware computing - HPPAC Ieee International Symposium On Parallel and Distributed Processing Workshops and Phd Forum. 795. DOI: 10.1109/IPDPS.2011.401  0.312
2010 Jiménez V, Cazorla FJ, Gioiosa R, Valero M, Boneti C, Kursun E, Cher CY, Isci C, Buyuktosunoglu A, Bose P. Power and thermal characterization of POWER6 system Parallel Architectures and Compilation Techniques - Conference Proceedings, Pact. 7-18. DOI: 10.1145/1854273.1854281  0.334
2010 Jiménez V, Gioiosa R, Kursun E, Cazorla FJ, Cher CY, Buyuktosunoglu A, Bose P, Valero M. Trends and techniques for energy efficient architectures Proceedings of the 2010 18th Ieee/Ifip International Conference On Vlsi and System-On-Chip, Vlsi-Soc 2010. 276-279. DOI: 10.1109/VLSISOC.2010.5642673  0.405
2009 Kursun E, Cher CY. Temperature variation characterization and thermal management of multicore architectures Ieee Micro. 29: 116-126. DOI: 10.1109/Mm.2009.18  0.354
2008 Cher CY, Gschwind M. Cell GC: Using the cell synergistic processor as a garbage collection coprocessor Vee'08 - Proceedings of the 4th International Conference On Virtual Execution Environments. 141-150. DOI: 10.1145/1346256.1346276  0.402
2008 Boneti C, Cazorla FJ, Gioiosa R, Buyuktosunoglu A, Cher CY, Valero M. Software-controlled priority characterization of POWERS processor Proceedings - International Symposium On Computer Architecture. 415-426. DOI: 10.1109/ISCA.2008.8  0.365
2006 Isci C, Buyuktosunoglu A, Cher CY, Bose P, Martonosi M. An analysis of efficient multi-core global power management policies: Maximizing performance for a given power budget Proceedings of the Annual International Symposium On Microarchitecture, Micro. 347-358. DOI: 10.1109/MICRO.2006.8  0.317
2006 Cher CY, Park I, Vijaykumar TN. Do trace cache, value prediction and prefetching improve SMT throughput? Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 3894: 232-251. DOI: 10.1007/11682127_17  0.523
2005 Li H, Cher CY, Roy K, Vijaykumar TN. Combined circuit and architectural level variable supply-voltage scaling for low power Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 13: 564-575. DOI: 10.1109/Tvlsi.2005.844295  0.601
2004 Cher CY, Hosking AL, Vijaykumar TN. Software prefetching for mark-sweep garbage collection: Hardware analysis and software redesign Acm Sigplan Notices. 39: 199-210. DOI: 10.1145/1037949.1024417  0.542
2003 Li H, Cher CY, Vijaykumar TN, Roy K. VSV: L2-miss-driven variable supply-voltage scaling for low power Proceedings of the Annual International Symposium On Microarchitecture, Micro. 2003: 19-28. DOI: 10.1109/MICRO.2003.1253180  0.603
2001 Cher CY, Vijaykumar TN. Skipper: A microarchitecture for exploiting control-flow independence Proceedings of the Annual International Symposium On Microarchitecture. 4-15.  0.524
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