| Year |
Citation |
Score |
| 2018 |
Alpman E, Khairi A, Dorrance R, Park M, Somayazulu VS, Foerster JR, Ravi A, Paramesh J, Pellerano S. 802.11g/n Compliant Fully Integrated Wake-Up Receiver With −72-dBm Sensitivity in 14-nm FinFET CMOS Ieee Journal of Solid-State Circuits. 53: 1411-1422. DOI: 10.1109/Jssc.2018.2817603 |
0.427 |
|
| 2016 |
Weng CH, Wei TA, Alpman E, Fu CT, Lin TH. A Continuous-Time Delta-Sigma Modulator Using ELD-Compensation-Embedded SAB and DWA-Inherent Time-Domain Quantizer Ieee Journal of Solid-State Circuits. DOI: 10.1109/Jssc.2016.2532345 |
0.417 |
|
| 2016 |
Weng CH, Huang WH, Alpman E, Lin TH. A 13-MHz 68-dB SNDR CTDSM using SAB loop filter and interpolating flash quantizer with random-skip IDWA function in 90-nm CMOS 2015 Ieee Asian Solid-State Circuits Conference, a-Sscc 2015 - Proceedings. DOI: 10.1109/ASSCC.2015.7387507 |
0.321 |
|
| 2015 |
Kundu S, Alpman E, Lu JHL, Lakdawala H, Paramesh J, Jung B, Zur S, Gordon E. A 1.2 v 2.64 GS/s 8 bit 39 mW Skew-Tolerant Time-interleaved SAR ADC in 40 nm Digital LP CMOS for 60 GHz WLAN Ieee Transactions On Circuits and Systems I: Regular Papers. 62: 1929-1939. DOI: 10.1109/Tcsi.2015.2452372 |
0.492 |
|
| 2014 |
Weng CH, Wei TA, Alpman E, Fu CT, Tseng YT, Lin TH. An 8.5MHz 67.2dB SNDR CTDSM with ELD compensation embedded twin-T SAB and circular TDC-based quantizer in 90nm CMOS Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. DOI: 10.1109/VLSIC.2014.6858398 |
0.376 |
|
| 2014 |
Kundu S, Lu JH, Alpman E, Lakdawala H, Paramesh J, Jung B, Zur S, Gordon E. A 1.2 v 2.64 GS/s 8bit 39 mW skew-tolerant time-interleaved SAR ADC in 40 nm digital LP CMOS for 60 GHz WLAN Proceedings of the Ieee 2014 Custom Integrated Circuits Conference, Cicc 2014. DOI: 10.1109/CICC.2014.6945992 |
0.531 |
|
| 2013 |
Lakdawala H, Schaecher M, Fu CT, Limaye R, Duster J, Tan Y, Balankutty A, Alpman E, Lee CC, Nguyen KM, Lee HJ, Ravi A, Suzuki S, Carlton BR, Kim HS, et al. A 32 nm SoC with dual core ATOM processor and RF wifi transceiver Ieee Journal of Solid-State Circuits. 48: 91-103. DOI: 10.1109/Jssc.2012.2222812 |
0.406 |
|
| 2013 |
Lee CC, Alpman E, Weaver S, Lu CY, Rizk J. A 66dB SNDR 15MHz BW SAR assisted ΔΣ ADC in 22nm tri-gate CMOS Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. |
0.453 |
|
| 2012 |
Tan Y, Duster J, Fu CT, Alpman E, Balankutty A, Lee C, Ravi A, Pellerano S, Chandrashekar K, Kim H, Carlton B, Suzuki S, Shafi M, Palaskas Y, Lakdawala H. A 2.4GHz WLAN transceiver with fully-integrated highly-linear 1.8V 28.4dBm PA, 34dBm T/R switch, 240MS/s DAC, 320MS/s ADC, and DPLL in 32nm SoC CMOS Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 76-77. DOI: 10.1109/VLSIC.2012.6243797 |
0.34 |
|
| 2012 |
Lakdawala H, Schaecher M, Fu CT, Limaye R, Duster J, Tan Y, Balankutty A, Alpman E, Lee C, Suzuki S, Carlton B, Kim HS, Verhelst M, Pellerano S, Kim T, et al. 32nm x86 OS-compliant PC on-chip with dual-core Atom® processor and RF WiFi transceiver Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 55: 62-63. DOI: 10.1109/ISSCC.2012.6176879 |
0.374 |
|
| 2011 |
Carlton BR, Lakdawala H, Alpman E, Rizk J, William Li Y, Perez-Esparza B, Rivera V, Nieva CF, Gordon E, Hackney P, Jan CH, Young IA, Soumyanath K. A 32nm, 1.05V, BIST enabled, 10-40MHz, 11-9 bit, 0.13mm 2 digitized integrator MASH ΔΣ ADC Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 36-37. |
0.382 |
|
| 2009 |
Alpman E, Lakdawala H, Carley LR, Soumyanath K. A 1.1V 50mW 2.5GS/s 7b time-interleaved C-2C SAR ADC in 45nm LP digital CMOS Digest of Technical Papers - Ieee International Solid-State Circuits Conference. DOI: 10.1109/ISSCC.2009.4977315 |
0.336 |
|
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