| Year |
Citation |
Score |
| 2013 |
Seiculescu C, Rahmati D, Murali S, Sarbazi-Azad H, Benini L, Micheli GD. Designing best effort networks-on-chip to meet hard latency constraints Transactions On Embedded Computing Systems. 12. DOI: 10.1145/2485984.2485996 |
0.42 |
|
| 2013 |
Rahmati D, Murali S, Benini L, Angiolini F, De Micheli G, Sarbazi-Azad H. Computing accurate performance bounds for best effort networks-on-chip Ieee Transactions On Computers. 62: 452-467. DOI: 10.1109/Tc.2011.240 |
0.423 |
|
| 2012 |
Kumar M, Murali S, Veezhinathan K. Network-on-chips on 3-D ICs: Past, present, and future Iete Technical Review. 29: 318. DOI: 10.4103/0256-4602.101313 |
0.375 |
|
| 2012 |
Kumar AS, Kumar MP, Murali S, Kamakoti V, Benini L, De Micheli G. A Buffer-Sizing Algorithm for Network-on-Chips with Multiple Voltage-Frequency Islands Journal of Electrical and Computer Engineering. 2012: 1-12. DOI: 10.1155/2012/537286 |
0.367 |
|
| 2010 |
Seiculescu C, Murali S, Benini L, De Micheli G. SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3-D Systems on Chips Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 1987-2000. DOI: 10.1109/Tcad.2010.2061610 |
0.361 |
|
| 2009 |
Mutapcic A, Boyd S, Murali S, Atienza D, De Micheli G, Gupta R. Processor speed control with thermal constraints Ieee Transactions On Circuits and Systems I: Regular Papers. 56: 1994-2008. DOI: 10.1109/Tcsi.2008.2011589 |
0.35 |
|
| 2009 |
Murali S. Designing reliable and efficient networks on chips Lecture Notes in Electrical Engineering. 34: 1-204. DOI: 10.1007/978-1-4020-9757-7_1 |
0.303 |
|
| 2008 |
Atienza D, Angiolini F, Murali S, Pullini A, Benini L, De Micheli G. Network-on-Chip design and synthesis outlook Integration. 41: 340-359. DOI: 10.1016/J.Vlsi.2007.12.002 |
0.445 |
|
| 2007 |
Murali S, Atienza D, Benini L, De Micheli G. A Method for Routing Packets Across Multiple Paths in NoCs with In-Order Delivery and Fault-Tolerance Gaurantees Vlsi Design. 2007: 1-11. DOI: 10.1155/2007/37627 |
0.399 |
|
| 2007 |
Murali S, Atienza D, Meloni P, Carta S, Benini L, De Micheli G, Raffo L. Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 15: 869-880. DOI: 10.1109/Tvlsi.2007.900742 |
0.433 |
|
| 2007 |
Tamhankar R, Murali S, Stergiou S, Pullini A, Angiolini F, Benini L, De Micheli G. Timing-Error-Tolerant Network-on-Chip Design Methodology Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 1297-1310. DOI: 10.1109/Tcad.2007.891371 |
0.397 |
|
| 2007 |
Murali S, Benini L, De Micheli G. An Application-Specific Design Methodology for On-Chip Crossbar Generation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 1283-1296. DOI: 10.1109/Tcad.2006.888284 |
0.405 |
|
| 2007 |
Pullini A, Angiolini F, Murali S, Atienza D, De Micheli G, Benini L. Bringing NoCs to 65 nm Ieee Micro. 27: 75-85. DOI: 10.1109/Mm.2007.79 |
0.389 |
|
| 2005 |
Bertozzi D, Jalabert A, Murali S, Tamhankar R, Stergiou S, Benini L, Micheli GD. NoC synthesis flow for customized domain specific multiprocessor systems-on-chip Ieee Transactions On Parallel and Distributed Systems. 16: 113-129. DOI: 10.1109/Tpds.2005.22 |
0.443 |
|
| 2005 |
Murali S, Theocharides T, Vijaykrishnan N, Irwin M, Benini L, De Micheli G. Analysis of Error Recovery Schemes for Networks on Chips Ieee Design and Test of Computers. 22: 434-442. DOI: 10.1109/Mdt.2005.104 |
0.308 |
|
| 2005 |
Murali S, De Micheli G. An application-specific design methodology for STbus crossbar generation Proceedings -Design, Automation and Test in Europe, Date '05. 1176-1181. DOI: 10.1109/DATE.2005.50 |
0.33 |
|
| 2004 |
Murali S, De Micheli G. SUNMAP: A tool for automatic topology selection and generation for NoCs Proceedings - Design Automation Conference. 914-919. DOI: 10.1109/DAC.2004.239780 |
0.319 |
|
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