| Year |
Citation |
Score |
| 2020 |
Kim R, Avci UE, Young IA. Computational Study of Temperature Effects on MOSFET Channel Material Benchmarking Ieee Electron Device Letters. 41: 1332-1335. DOI: 10.1109/Led.2020.3012187 |
0.421 |
|
| 2020 |
Kim R, Avci UE, Young IA. Comprehensive n- and pMOSFET Channel Material Benchmarking and Analysis of CMOS Performance Metrics Considering Quantum Transport and Carrier Scattering Effects Ieee Journal of the Electron Devices Society. 8: 505-523. DOI: 10.1109/Jeds.2020.2991677 |
0.443 |
|
| 2019 |
Kim R, Avci UE, Young IA. Computational Study of Geometrical Designs for Source/Drain Contacts to Reduce Parasitic Resistance in Extremely Scaled MOSFETs Ieee Transactions On Electron Devices. 66: 1189-1196. DOI: 10.1109/Ted.2019.2892783 |
0.352 |
|
| 2018 |
Vaidyanathan K, Morris DH, Avci UE, Liu H, Karnik T, Wang H, Young IA. Improving Energy Efficiency of Low-Voltage Logic by Technology-Driven Design Ieee Journal On Exploratory Solid-State Computational Devices and Circuits. 4: 10-18. DOI: 10.1109/Jxcdc.2018.2812242 |
0.4 |
|
| 2018 |
Chang S, Avci UE, Nikonov DE, Manipatruni S, Young IA. Physical Origin of Transient Negative Capacitance in a Ferroelectric Capacitor Physical Review Applied. 9: 14010. DOI: 10.1103/Physrevapplied.9.014010 |
0.306 |
|
| 2017 |
Chang S, Avci UE, Nikonov DE, Young IA. A Thermodynamic Perspective of Negative-Capacitance Field-Effect Transistors Ieee Journal On Exploratory Solid-State Computational Devices and Circuits. 3: 56-64. DOI: 10.1109/Jxcdc.2017.2750108 |
0.318 |
|
| 2015 |
Kim R, Avci UE, Young IA. Comprehensive Performance Benchmarking of III-V and Si nMOSFETs (Gate Length} = 13 nm) Considering Supply Voltage and OFF-Current Ieee Transactions On Electron Devices. DOI: 10.1109/Ted.2015.2388708 |
0.456 |
|
| 2015 |
Kim R, Avci UE, Young IA. Ge Nanowire nMOSFET Design with Optimum Band Structure for High Ballistic Drive Current Ieee Electron Device Letters. 36: 751-753. DOI: 10.1109/Led.2015.2445915 |
0.416 |
|
| 2015 |
Avci UE, Morris DH, Young IA. Tunnel field-effect transistors: Prospects and challenges Ieee Journal of the Electron Devices Society. 3: 88-95. DOI: 10.1109/Jeds.2015.2390591 |
0.4 |
|
| 2015 |
Kim R, Avci UE, Young IA. Source/drain doping effects and performance analysis of ballistic III-V n-MOSFETs Ieee Journal of the Electron Devices Society. 3: 37-43. DOI: 10.1109/Jeds.2014.2363389 |
0.418 |
|
| 2014 |
Morris DH, Avci UE, Rios R, Young IA. Design of low voltage tunneling-FET logic circuits considering asymmetric conduction characteristics Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 4: 380-388. DOI: 10.1109/Jetcas.2014.2361054 |
0.422 |
|
| 2013 |
Kotlyar R, Avci UE, Cea S, Rios R, Linton TD, Kuhn KJ, Young IA. Bandgap engineering of group IV materials for complementary n and p tunneling field effect transistors Applied Physics Letters. 102. DOI: 10.1063/1.4798283 |
0.331 |
|
| 2012 |
Avci UE, Kencke DL, Chang PLD. Floating-body diode-a novel DRAM device Ieee Electron Device Letters. 33: 161-163. DOI: 10.1109/Led.2011.2177239 |
0.408 |
|
| 2007 |
LIN H, LIU H, KUMAR A, AVCI U, VAN DELDEN JS, TIWARI S. POWER ADAPTIVE CONTROL OF DENSE CONFIGURED SUPER-SELF-ALIGNED BACK-GATE PLANAR TRANSISTORS International Journal of High Speed Electronics and Systems. 17: 143-146. DOI: 10.1142/S0129156407004357 |
0.605 |
|
| 2007 |
Lin H, Liu H, Kumar A, Avci U, Delden JSV, Tiwari S. Strained-Si Channel Super-Self-Aligned Back-Gate/Double-Gate Planar Transistors Ieee Electron Device Letters. 28: 506-508. DOI: 10.1109/Led.2007.896896 |
0.621 |
|
| 2006 |
Lin H, Liu H, Kumar A, Avci U, Van Delden JS, Tiwari S. Super-self-aligned back-gate∕double-gate planar transistors: Novel fabrication approach Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures. 24: 3230. DOI: 10.1116/1.2397067 |
0.625 |
|
| 2005 |
Avci U, Tiwari S. A novel compact circuit for 4-PAM energy-efficient high speed interconnect data transmission and reception Microelectronics Journal. 36: 67-75. DOI: 10.1016/J.Mejo.2004.09.005 |
0.599 |
|
| 2004 |
Silva H, Kim MK, Avci U, Kumar A, Tiwari S. Nonvolatile Silicon Memory at the Nanoscale Mrs Bulletin. 29: 845-851. DOI: 10.1557/Mrs2004.239 |
0.584 |
|
| 2004 |
Avci U, Tiwari S. Nanoscale thin single-crystal silicon and its application to electronics Applied Physics Letters. 84: 2406-2408. DOI: 10.1063/1.1689745 |
0.559 |
|
| 2004 |
Avci U, Tiwari S. Back-gated MOSFETs with controlled silicon thickness for adaptive threshold-voltage control Electronics Letters. 40: 74-75. DOI: 10.1049/El:20040028 |
0.628 |
|
| 2003 |
Tiwari S, Avci UE, Liu CC, Xue L, Kumar A, Kim SK, Silva HG. Are we there yet? Looking beyond the end of scaling in the Nanometer Era Proceedings of Spie. 5118: 456-465. DOI: 10.1117/12.502018 |
0.564 |
|
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