☰

Jose G. Delgado-Frias, Ph.D. - Publications

Affiliations: 
1986-1988 Engineering Science University of Oxford, Oxford, United Kingdom 
 1989-2000 Electrical Engineering Binghamtom University 
 2001- School of Electrical Engineering and Computer Science Washington State University, Pullman, WA, United States 
Area:
Computer Architecture, VLSI Design, Validation,
Tree Info Similar researchers PubMed Report error

78 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Turi MA, Delgado-Frias JG. Effective Low Leakage 6T and 8T FinFET SRAMs: Using Cells With Reverse-Biased FinFETs, Near-Threshold Operation, and Power Gating Ieee Transactions On Circuits and Systems Ii: Express Briefs. 67: 765-769. DOI: 10.1109/Tcsii.2019.2922921  0.772
2020 Silva-Martinez J, Delgado-Frias J. MWSCAS Guest Editorial Special Issue Based on the 62nd International Midwest Symposium on Circuits and Systems Ieee Transactions On Circuits and Systems I: Regular Papers. 67: 3249-3250. DOI: 10.1109/TCSI.2020.3016577  0.541
2020 Liu R, Delgado-Frias JG, Boyce D, Qian Y, Khanna R. Online Firmware Functional Validation Scheme Using Colored Petri Net Model Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 39: 1532-1545. DOI: 10.1109/Tcad.2019.2912919  0.623
2017 Turi MA, Delgado-Frias JG. Full-VDD and near-threshold performance of 8T FinFET SRAM cells Integration. 57: 169-183. DOI: 10.1016/J.Vlsi.2016.12.003  0.78
2016 Cree JV, Delgado-Frias J. Autonomous management of a recursive area hierarchy for large scale wireless sensor networks using multiple parents Ad Hoc Networks. 39: 1-22. DOI: 10.1016/j.adhoc.2014.02.004  0.577
2015 Liu R, Delgado-Frias JG, Boyce D, Khanna R. UEFI USB bus initialization verification using Colored Petri Net Midwest Symposium On Circuits and Systems. 2015. DOI: 10.1109/MWSCAS.2015.7282158  0.601
2015 Delgado-Frias JG, Zhang Z, Turi MA. Near-threshold CNTFET SRAM cell design with removed metallic CNT tolerance Proceedings - Ieee International Symposium On Circuits and Systems. 2015: 2928-2931. DOI: 10.1109/ISCAS.2015.7169300  0.568
2014 Zhang Z, Delgado-Frias JG. Near-threshold CNTFET SRAM cell design with word-line boosting and removed metallic CNT tolerance Ieee Transactions On Nanotechnology. 13: 182-191. DOI: 10.1109/Tnano.2013.2295757  0.649
2014 Turi MA, Delgado-Frias JG. An evaluation of 6T and 8T FinFET SRAM cell leakage currents Midwest Symposium On Circuits and Systems. 523-526. DOI: 10.1109/MWSCAS.2014.6908467  0.61
2014 Silva-Martinez J, Sanchez-Sinencio E, Delgado-Frias J, Geiger RL. Welcome to MWSCAS 2014 Midwest Symposium On Circuits and Systems. DOI: 10.1109/MWSCAS.2014.6908327  0.584
2013 Zhang Z, Delgado-Frias JG. Near-threshold CNTFET SRAM cell design with gated cell power supply Midwest Symposium On Circuits and Systems. 340-343. DOI: 10.1109/MWSCAS.2013.6674655  0.581
2013 Zhang Z, Delgado-Frias JG. CNTFET 8T SRAM cell performance with near-threshold power supply scaling Proceedings - Ieee International Symposium On Circuits and Systems. 2123-2126. DOI: 10.1109/ISCAS.2013.6572293  0.586
2013 Cree JV, Delgado-Frias J. Management of large-scale wireless sensor networks utilizing multi-parent recursive area hierarchies 2013 International Green Computing Conference Proceedings, Igcc 2013. DOI: 10.1109/IGCC.2013.6604473  0.57
2012 Zhang Z, Turi MA, Delgado-Frias JG. SRAM leakage in CMOS, FinFET and CNTFET technologies Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 267-270. DOI: 10.1145/2206781.2206846  0.59
2012 Zhang Z, Delgado-Frias JG. Carbon nanotube SRAM design with metallic CNT or removed metallic CNT tolerant approaches Ieee Transactions On Nanotechnology. 11: 788-798. DOI: 10.1109/Tnano.2012.2197636  0.638
2012 Gerik CM, Turi MA, Delgado-Frias JG. FinFET 3T and 3T1D dynamic RAM cells Midwest Symposium On Circuits and Systems. 454-457. DOI: 10.1109/MWSCAS.2012.6292055  0.569
2012 Van Dyken J, Delgado-Frias JG. A superscalar processor for a medium-grain reconfigurable hardware Midwest Symposium On Circuits and Systems. 426-429. DOI: 10.1109/MWSCAS.2012.6292048  0.55
2012 Cree JV, Delgado-Frias J, Hughes M, Burghard B, Silvers K. NOA: A scalable multi-parent clustering hierarchy for WSNs Procedia Computer Science. 10: 1140-1145. DOI: 10.1016/J.Procs.2012.06.163  0.58
2011 Zhang Z, Delgado-Frias JG. Low power and metallic CNT tolerant CNTFET SRAM design Proceedings of the Ieee Conference On Nanotechnology. 1177-1182. DOI: 10.1109/NANO.2011.6144323  0.601
2011 Grigoleit F, Delgado-Frias JG, Zhang Z. CNTFET gate design with tolerance to metallic CNTs Midwest Symposium On Circuits and Systems. DOI: 10.1109/MWSCAS.2011.6026573  0.54
2011 Dyken JV, Delgado-Frias JG. A medium-grain reconfigurable processor organization Midwest Symposium On Circuits and Systems. DOI: 10.1109/MWSCAS.2011.6026460  0.599
2011 Turi MA, Delgado-Frias JG. Performance-power tradeoffs of 8T FinFET SRAM cells Midwest Symposium On Circuits and Systems. DOI: 10.1109/MWSCAS.2011.6026404  0.627
2011 Munson PM, Delgado-Frias JG. A performance-power evaluation of FinFET flip-flops under process variations Midwest Symposium On Circuits and Systems. DOI: 10.1109/MWSCAS.2011.6026271  0.599
2010 Turi MA, Delgado-Frias JG, Jha NK. Low-power FinFET design schemes for NOR address decoders Proceedings of 2010 International Symposium On Vlsi Design, Automation and Test, Vlsi-Dat 2010. 74-77. DOI: 10.1109/VDAT.2010.5496695  0.623
2010 Ramirez-Conejo G, Diaz-Carmona J, Ramirez-Agundis A, Padilla-Medina A, Delgado-Frias J. FPGA implementation of adjustable wideband fractional delay FIR filters Proceedings - 2010 International Conference On Reconfigurable Computing and Fpgas, Reconfig 2010. 406-411. DOI: 10.1109/ReConFig.2010.68  0.56
2010 Zhang Z, Delgado-Frias JG, Nyathi J. CNTFET SRAM cell design with tolerance to metallic CNTs Midwest Symposium On Circuits and Systems. 1105-1108. DOI: 10.1109/MWSCAS.2010.5548846  0.769
2010 Liu J, Delgado-Frias JG, Wang X. A novel analytical model for wormhole switching network on chip with adaptive routing Midwest Symposium On Circuits and Systems. 733-736. DOI: 10.1109/MWSCAS.2010.5548715  0.585
2010 Van Dyken J, Delgado-Frias JG. A medium-grain reconfigurable processing unit Midwest Symposium On Circuits and Systems. 729-732. DOI: 10.1109/MWSCAS.2010.5548714  0.513
2010 Delgado-Frias JG, Palomera-García R, Nyathi J. Welcome to the 53rd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2010) Midwest Symposium On Circuits and Systems. DOI: 10.1109/MWSCAS.2010.5548596  0.759
2010 Van Dyken J, Delgado-Frias JG. FPGA schemes for minimizing the power-throughput trade-off in executing the Advanced Encryption Standard algorithm Journal of Systems Architecture. 56: 116-123. DOI: 10.1016/J.Sysarc.2009.12.001  0.66
2009 Blum DR, Delgado-Frias JG. Delay and energy analysis of SEU and EET-tolerant pipeline latches and flip-flops Ieee Transactions On Nuclear Science. 56: 1618-1628. DOI: 10.1109/Tns.2009.2019590  0.644
2009 Zhang Z, Liu Y, Nyathi J, Delgado-Frias JG. Performance of CNFET SRAM cells under diameter variation corners Midwest Symposium On Circuits and Systems. 547-550. DOI: 10.1109/MWSCAS.2009.5236035  0.754
2009 Guo R, Delgado-Frias JG. IP Routing table compaction and sampling schemes to enhance TCAM cache performance Journal of Systems Architecture. 55: 61-69. DOI: 10.1016/J.Sysarc.2008.08.001  0.812
2009 Turi MA, Delgado-Frias JG. Decreasing energy consumption in address decoders by means of selective precharge schemes Microelectronics Journal. 40: 1590-1600. DOI: 10.1016/J.Mejo.2009.03.008  0.776
2008 Myjak MJ, Delgado-Frias JG. A medium-grain reconfigurable architecture for DSP: VLSI design, benchmark mapping, and performance Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 16: 14-23. DOI: 10.1109/Tvlsi.2007.912080  0.794
2008 Turi MA, Delgado-Frias JG. High-performance low-power selective precharge schemes for address decoders Ieee Transactions On Circuits and Systems Ii: Express Briefs. 55: 917-921. DOI: 10.1109/Tcsii.2008.923435  0.79
2008 Turi MA, Delgado-Frias JG. High-performance low-power AND and Sense-Amp address decoders with selective precharging Proceedings - Ieee International Symposium On Circuits and Systems. 1464-1467. DOI: 10.1109/ISCAS.2008.4541705  0.621
2008 Zhao L, Delgado-Frias JG, Sivakumar K. Performance analysis of multipath transmission over 802.11-based multihop ad hoc networks: A cross-layer perspective Iet Communications. 2: 380-387. DOI: 10.1049/Iet-Com:20070002  0.642
2008 Sapaty P, Sugisaka M, Delgado-Frias J, Filipe J, Mirenkov N. Intelligent management of distributed dynamic sensor networks Artificial Life and Robotics. 12: 81-87. DOI: 10.1007/S10015-007-0446-8  0.589
2007 He R, Delgado-Frias JG. Fault tolerant interleaved switching fabrics for scalable high-performance routers Ieee Transactions On Parallel and Distributed Systems. 18: 1727-1739. DOI: 10.1109/Tpds.2007.1109  0.765
2007 Myjak MJ, Delgado-Frias JG. Medium-grain cells for reconfigurable DSP hardware Ieee Transactions On Circuits and Systems I: Regular Papers. 54: 1255-1265. DOI: 10.1109/Tcsi.2007.895384  0.798
2007 Zhao L, Delgado-Frias JG. Performance analysis of multipath data transmission in multihop ad hoc networks 2006 3rd Annual Ieee Communications Society On Sensor and Adhoc Communications and Networks, Secon 2006. 3: 927-932. DOI: 10.1109/SAHCN.2006.288584  0.58
2007 Hongxun L, Delgado-Frias JG, Medidi S. Using a cache scheme to detect misbehaving nodes in mobile ad-hoc networks Icon 2007 - Proceedings of the 2007 15th Ieee International Conference On Networks. 7-12. DOI: 10.1109/ICON.2007.4444053  0.591
2007 He R, Delgado-Frias JG. Redundant array of independent fabrics -an architecture for next generation network Globecom - Ieee Global Telecommunications Conference. 2763-2768. DOI: 10.1109/GLOCOM.2007.523  0.618
2007 Zhao L, Delgado-Frias JG. MARS: Misbehavior detection in ad hoc networks Globecom - Ieee Global Telecommunications Conference. 941-945. DOI: 10.1109/GLOCOM.2007.181  0.607
2007 Yang LT, Delgado-Frias JG, Li Y, Niamat M, Soudris D, Vemuru SR. Preface Integration, the Vlsi Journal. 40: 61. DOI: 10.1016/j.vlsi.2006.11.001  0.452
2007 Yang LT, Delgado-Frias JG, Li Y, Niamat M, Soudris D, Vemuru SR. Preface of Special Issue on VLSI Design and Test Microelectronic Engineering. 84: 193. DOI: 10.1016/J.Mee.2006.12.005  0.578
2007 Sapaty P, Sugisaka M, Finkelstein R, Delgado-Frias J, Mirenkov N. Emergent societies: Advanced IT support of crisis relief missions Artificial Life and Robotics. 11: 116-122. DOI: 10.1007/S10015-006-0412-X  0.581
2007 Medidi S, Delgado-Frias JG, Liu H. Hardware/software solution to improve security in mobile Ad-hoc networks Mobile and Wireless Network Security and Privacy. 205-217. DOI: 10.1007/978-0-387-71058-7_10  0.577
2006 Li Z, Delgado-Frias JG. Multipath routing based secure data transmission in ad hoc networks Ieee International Conference On Wireless and Mobile Computing, Networking and Communications 2006, Wimob 2006. 17-23. DOI: 10.1109/WIMOB.2006.1696359  0.598
2006 Blum DR, Delgado-Frias JG. Schemes for eliminating transient-width clock overhead from SET-tolerant memory-based systems Ieee Transactions On Nuclear Science. 53: 1567-1573. DOI: 10.1109/Tns.2006.874496  0.629
2006 Tatapudi SB, Delgado-Frias JG. A mesochronous pipelining scheme for high-performance digital systems Ieee Transactions On Circuits and Systems I: Regular Papers. 53: 1078-1088. DOI: 10.1109/TCSI.2006.870221  0.643
2006 Tatapudi SB, Delgado-Frias JG. A mesochronous pipelining scheme for high-performance digital systems Ieee Transactions On Circuits and Systems I. 53: 1078-1088. DOI: 10.1109/Tcsi.2006.870221  0.788
2006 He R, Delgado-Frias JG. Interleaved multistage switching fabrics for scalable high performance routers Globecom - Ieee Global Telecommunications Conference. DOI: 10.1109/GLOCOM.2006.341  0.622
2005 Delgado-Frias JG, Nyathi J, Tatapudi SB. Decoupled dynamic ternary content addressable memories Ieee Transactions On Circuits and Systems I: Regular Papers. 52: 2139-2147. DOI: 10.1109/Tcsi.2005.853358  0.761
2005 Tatapudi SB, Delgado-Frias JG. A high performance hybrid wave-pipelined multiplier Proceedings - Ieee Computer Society Annual Symposium On Vlsi - New Frontiers in Vlsi. 282-283. DOI: 10.1109/ISVLSI.2005.7  0.578
2005 Rydberg RR, Nyathi J, Delgado-Frias JG. A distributed FIFO scheme for on chip communication Proceedings - Ieee International Symposium On Circuits and Systems. 1851-1854. DOI: 10.1109/ISCAS.2005.1464971  0.788
2004 Rooney JJ, Delgado-Frias JG, Summerville DH. Associative ternary cache for IP routing Iee Proceedings: Computers and Digital Techniques. 151: 409-416. DOI: 10.1049/ip-cdt:20041014  0.695
2003 Delgado-Frias JG, Ratanpal GB. A VLSI crossbar switch with wrapped wave front arbitration Ieee Transactions On Circuits and Systems I: Fundamental Theory and Applications. 50: 135-141. DOI: 10.1109/Tcsi.2002.807518  0.647
2003 Myjak MJ, Delgado-Frias JG. A Two-Level Reconfigurable Architecture for Digital Signal Processing Proceedings of the International Conference On Vlsi. 21-27. DOI: 10.1016/J.Mee.2006.02.008  0.797
2002 Nyathi J, Delgado-Frias JG. A hybrid wave pipelined network router Ieee Transactions On Circuits and Systems I: Fundamental Theory and Applications. 49: 1764-1772. DOI: 10.1109/Tcsi.2002.805705  0.773
2000 Vassiliadis S, Zhang M, Delgado-Frias JG. Elementary function generators for neural-network emulators. Ieee Transactions On Neural Networks / a Publication of the Ieee Neural Networks Council. 11: 1438-49. PMID 18249867 DOI: 10.1109/72.883475  0.755
2000 Delgado-Frias JG, Nyathi J. A high-performance encoder with priority lookahead Ieee Transactions On Circuits and Systems I: Fundamental Theory and Applications. 47: 1390-1393. DOI: 10.1109/81.883335  0.809
1999 Aikens II VC, Delgado-Frias JG, Pechanek GG, Vassiliadis S. A neuro-emulator with embedded capabilities for generalized learning Journal of Systems Architecture. 45: 1219-1243. DOI: 10.1016/S1383-7621(98)00032-0  0.76
1998 Harvin AE, Delgado-Frias JG. Dictionary machine emulation on a VLSI computing tree system Proceedings of the Ieee Great Lakes Symposium On Vlsi. 134-139. DOI: 10.1109/GLSV.1998.665213  0.596
1998 Delgado-Frias JG, Nyathi J, Summerville DH. A programmable dynamic interconnection network router with hidden refresh Ieee Transactions On Circuits and Systems I: Fundamental Theory and Applications. 45: 1182-1190. DOI: 10.1109/81.735440  0.821
1998 Summerville DH, Delgado-Frias JG, Vassiliadis S. Executing tree routing algorithms on a high-performance pattern associative router Journal of Systems Architecture. 44: 849-866. DOI: 10.1016/S1383-7621(97)00050-7  0.749
1996 Summerville DH, Delgado-Frias JG, Vassiliadis S. A flexible bit-pattern associative router for interconnection networks Ieee Transactions On Parallel and Distributed Systems. 7: 477-485. DOI: 10.1109/71.503772  0.739
1996 Zhang M, Vassiliadis S, Delgado-Frias JG. Sigmoid generators for neural computing using piecewise approximations Ieee Transactions On Computers. 45: 1045-1049. DOI: 10.1109/12.537127  0.745
1995 Park J, Vassiliadis S, Delgado-Frias JG. Flexible oblivious router architecture Ibm Journal of Research and Development. 39: 315-329. DOI: 10.1147/Rd.393.0315  0.767
1995 Lin W, Delgado-Frias JG, Gause DC, Vassiliadis S. Hybrid newton-raphson genetic algorithm for the traveling salesman problem Cybernetics and Systems. 26: 387-412. DOI: 10.1080/01969729508927504  0.685
1995 Chu W, Vassiliadis S, Delgado-Frias J. The multi-associative branch target buffer: a cost effective BTB mechanism Microprocessing and Microprogramming. 41: 211-225. DOI: 10.1016/0165-6074(95)00009-D  0.716
1994 Zhang M, Delgado-Frias JG, Vassiliadis S. Table driven Newton scheme for high precision logarithm generation Iee Proceedings: Computers and Digital Techniques. 141: 281-292. DOI: 10.1049/ip-cdt:19941268  0.733
1994 Chang C, Vassiliadis S, Delgado-Frias J. An investigation of binary CLA and ripple CMOS adder designs Microprocessing and Microprogramming. 40: 1-21. DOI: 10.1016/0165-6074(94)90002-7  0.72
1993 VASSILIADIS S, PECHANEK GG, DELGADO-FRIAS JG. SPIN: THE SEQUENTIAL PIPELINED NEUROEMULATOR International Journal On Artificial Intelligence Tools. 2: 117-132. DOI: 10.1142/S0218213093000084  0.764
1992 Pechanek GG, Vassiliadis S, Delgado-Frias JG. Digital neural emulators using tree accumulation and communication structures. Ieee Transactions On Neural Networks / a Publication of the Ieee Neural Networks Council. 3: 934-50. PMID 18276490 DOI: 10.1109/72.165595  0.775
1992 DELGADO-FRIAS JG, VASSILIADIS S, GOSHTASBI J. SEMANTIC NETWORK ARCHITECTURES: AN EVALUATION International Journal On Artificial Intelligence Tools. 1: 57-83. DOI: 10.1142/S0218213092000132  0.72
1988 Delgado-Frias J, Moore WR. Parallel architectures for AI semantic network processing Knowledge-Based Systems. 1: 259-265. DOI: 10.1016/0950-7051(88)90079-2  0.75
Show low-probability matches.