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Erik Chmelar, Ph.D. - Publications

Affiliations: 
2004 Stanford University, Palo Alto, CA 
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4 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2012 Chmelar E, Ito C. Mostly digital SerDes: A comprehensive low power receiver architecture Designcon 2012: Where Chipheads Connect. 3: 1879-1918.  0.362
2008 Park I, Lee D, Chmelar E, McCluskey EJ. Inconsistent fails due to limited tester timing accuracy Proceedings of the Ieee Vlsi Test Symposium. 47-52. DOI: 10.1109/VTS.2008.23  0.625
2007 Al-Yamani A, Devta-Prasanna N, Chmelar E, Grinchuk M, Gunda A. Scan test cost and power reduction through systematic scan reconfiguration Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 907-918. DOI: 10.1109/Tcad.2006.884582  0.509
2005 Al-Yamani A, Chmelar E, Grinchuck M. Segmented addressable scan architecture Proceedings of the Ieee Vlsi Test Symposium. 405-411. DOI: 10.1109/VTS.2005.74  0.541
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