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Edward J. Mccluskey - Publications

Affiliations: 
Computer Science Stanford University, Palo Alto, CA 
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96 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2010 Al-Yamani AA, McCluskey EJ. Test set compression through alternation between deterministic and pseudorandom test patterns Journal of Electronic Testing: Theory and Applications (Jetta). 26: 513-521. DOI: 10.1007/S10836-010-5172-9  0.778
2008 Lee J, Park I, McCluskey EJ. Error sequence analysis Proceedings of the Ieee Vlsi Test Symposium. 255-260. DOI: 10.1109/VTS.2008.45  0.357
2008 Ferhani FF, Saxena NR, McCluskey EJ, Nigh P. How many test patterns are useless? Proceedings of the Ieee Vlsi Test Symposium. 23-28. DOI: 10.1109/VTS.2008.27  0.778
2008 Park I, Lee D, Chmelar E, McCluskey EJ. Inconsistent fails due to limited tester timing accuracy Proceedings of the Ieee Vlsi Test Symposium. 47-52. DOI: 10.1109/VTS.2008.23  0.778
2008 Park I, McCluskey EJ. Launch-on-shift-capture transition tests Proceedings - International Test Conference. DOI: 10.1109/TEST.2008.4700648  0.394
2008 Cho KY, Mitra S, McCluskey EJ. California scan architecture for high quality and low power testing Proceedings - International Test Conference. DOI: 10.1109/TEST.2007.4437634  0.36
2007 Cho KY, McCluskey EJ. Test set reordering using the gate exhaustive test metric Proceedings of the Ieee Vlsi Test Symposium. 199-204. DOI: 10.1109/VTS.2007.79  0.41
2007 Ferhani FF, McCluskey EJ. Classifying bad chips and ordering test sets Proceedings - International Test Conference. DOI: 10.1109/TEST.2006.297736  0.778
2005 Al-Yamani AA, McCluskey EJ. Test chip experimental results on high-level structural test Acm Transactions On Design Automation of Electronic Systems. 10: 690-701. DOI: 10.1145/1109118.1109125  0.794
2005 Park I, Al-Yamani A, McCluskey EJ. Effective TARO pattern generation Proceedings of the Ieee Vlsi Test Symposium. 161-166. DOI: 10.1109/VTS.2005.43  0.78
2005 Kyoung YC, Mitra S, McCluskey EJ. Gate exhaustive testing Proceedings - International Test Conference. 2005: 771-777. DOI: 10.1109/TEST.2005.1584040  0.484
2005 Li JCM, McCluskey EJ. Diagnosis of resistive-open and stuck-open defects in digital CMOS ICs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 1748-1758. DOI: 10.1109/TCAD.2005.852457  0.415
2005 Al-Yamani AA, Mitra S, McCluskey EJ. Optimized reseeding by seed ordering and encoding Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 264-270. DOI: 10.1109/Tcad.2004.840550  0.738
2005 Al-Yamani AA, McCluskey EJ. BIST-guided ATPG Proceedings - International Symposium On Quality Electronic Design, Isqed. 244-249. DOI: 10.1109/ISQED.2005.26  0.78
2004 Tahoori MB, McCluskey EJ, Renovell M, Faure P. A multi-configuration strategy for an application dependent testing of FPGAs Proceedings of the Ieee Vlsi Test Symposium. 154-159. DOI: 10.1109/VTEST.2004.1299239  0.386
2004 Mitra S, Volkerink E, McCluskey EJ, Eichenberger S. Delay defect screening using process monitor structures Proceedings of the Ieee Vlsi Test Symposium. 43-48. DOI: 10.1109/VTEST.2004.1299224  0.362
2004 McCluskey EJ, Al-Yamani A, Li JCM, Tseng CW, Volkerink E, Ferhani FF, Li E, Mitra S. ELF-Murphy data on defects and test sets Proceedings of the Ieee Vlsi Test Symposium. 16-22. DOI: 10.1109/VTEST.2004.1299220  0.789
2004 Al-Yamani A, McCluskey EJ. Test quality for high level structural test Proceedings - Ieee International High-Level Design Validation and Test Workshop, Hldvt. 109-114. DOI: 10.1109/HLDVT.2004.1431250  0.794
2004 McCluskey E. Digital integrated circuit testing for art historians and test experts Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 4.  0.38
2003 Al-Yamani AA, Mitra S, McCluskey EJ. BIST reseeding with very few seeds Proceedings of the Ieee Vlsi Test Symposium. 2003: 69-74. DOI: 10.1109/VTEST.2003.1197635  0.77
2003 Al-Yamani AA, McCluskey EJ. Built-in reseeding for serial BIST Proceedings of the Ieee Vlsi Test Symposium. 2003: 63-68. DOI: 10.1109/VTEST.2003.1197634  0.798
2003 Al-Yamani AA, McCluskey EJ. Seed encoding with LFSRs and cellular automata Proceedings - Design Automation Conference. 560-565.  0.762
2002 Mitra S, McCluskey EJ, Makar S. Design for testability and testing of IEEE 1149.1 TAP controller Proceedings of the Ieee Vlsi Test Symposium. 2002: 247-252. DOI: 10.1109/VTS.2002.1011145  0.403
2002 Li JCM, McCluskey EJ. Diagnosis of sequence-dependent chips Proceedings of the Ieee Vlsi Test Symposium. 2002: 187-192. DOI: 10.1109/VTS.2002.1011137  0.445
2002 Tseng CW, Li J, McCluskey EJ. Experimental results for slow-speed testing Proceedings of the Ieee Vlsi Test Symposium. 2002: 37-42. DOI: 10.1109/VTS.2002.1011108  0.39
2002 Al-Yamani AA, Mitra S, McCluskey EJ. Testing digital circuits with constraints Proceedings - Ieee International Symposium On Defect and Fault Tolerance in Vlsi Systems. 2002: 195-203. DOI: 10.1109/DFTVS.2002.1173516  0.779
2002 Lovellette MN, Wood KS, Wood DL, Beall JH, Shirvani PP, Oh N, McCluskey EJ. Strategies for fault-tolerant, space-based computing: Lessons learned from the ARGOS testbed Ieee Aerospace Conference Proceedings. 5: 2109-2119. DOI: 10.1109/AERO.2002.1035377  0.768
2002 Oh N, Shirvani PP, McCluskey EJ. Control-flow checking by software signatures Ieee Transactions On Reliability. 51: 111-122. DOI: 10.1109/24.994926  0.777
2002 Oh N, Shirvani PP, McCluskey EJ. Error detection by duplicated instructions in super-scalar processors Ieee Transactions On Reliability. 51: 63-75. DOI: 10.1109/24.994913  0.789
2002 Oh N, Mitra S, McCluskey EJ. ED 4I: Error detection by diverse data and duplicated instructions Ieee Transactions On Computers. 51: 180-199. DOI: 10.1109/12.980007  0.569
2002 Tahoori MB, Mitra S, Toutounchi S, McCluskey EJ. Fault grading FPGA interconnect test configurations Ieee International Test Conference (Tc). 608-617.  0.454
2001 Touba NA, McCluskey EJ. Bit-fixing in pseudorandom sequences for scan BIST Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 20: 545-555. DOI: 10.1109/43.918212  0.692
2001 Tseng CW, Mitra S, Davidson S, McCluskey EJ. An evaluation of pseudo random testing for detecting real defects Proceedings of the Ieee Vlsi Test Symposium. 404-409.  0.423
2001 Tseng CW, McCluskey EJ. Multiple-output propagation transition fault test Ieee International Test Conference (Tc). 358-366.  0.399
2001 Huang WJ, Mitra S, McCluskey EJ. Fast run-time fault location in dependable FPGA-based applications Ieee International Workshop On Defect and Fault Tolerance in Vlsi Systems. 206-214.  0.419
2001 Tseng CW, Chen R, Nigh P, McCluskey EJ. MINVDD testing for weak CMOS ICs Proceedings of the Ieee Vlsi Test Symposium. 339-344.  0.395
2001 Al-Yamani AA, Oh N, McCluskey EJ. Performance evaluation of checksum-based ABFT Ieee International Workshop On Defect and Fault Tolerance in Vlsi Systems. 461-466.  0.693
2001 Huang WJ, McCluskey EJ. Column-Based Precompiled Configuration Techniques for FPGA Proceedings - 9th Annual Ieee Symposium On Field-Programmable Custom Computing Machines, Fccm 2001. 137-146.  0.414
2001 Yu SY, McCluskey EJ. Permanent fault repair for FPGAs with limited redundant area Ieee International Workshop On Defect and Fault Tolerance in Vlsi Systems. 125-133.  0.344
2001 McCluskey EJ. Guaranteeing quality throughout the product life cycle: On-line test and repair to the rescue Proceedings of the Ieee Vlsi Test Symposium. 151.  0.327
2001 Li JCM, McCluskey EJ. Diagnosis of tunneling opens Proceedings of the Ieee Vlsi Test Symposium. 22-27.  0.366
2000 Saxena NR, Fernandez-Gomez S, Huang WJ, Mitra S, Yu SY, McCluskey EJ. Dependable computing and online testing in adaptive and configurable systems Ieee Design and Test of Computers. 17: 29-41. DOI: 10.1109/54.825675  0.731
2000 Shirvani PP, Saxena NR, McCluskey EJ. Software-implemented EDAC protection against SEUs Ieee Transactions On Reliability. 49: 273-284. DOI: 10.1109/24.914544  0.764
2000 McCluskey EJ, Tseng CW. Stuck-fault tests vs. actual defects Ieee International Test Conference (Tc). 336-343.  0.524
2000 Tseng CW, McCluskey EJ, Shao X, Wu DM. Cold delay defect screening Proceedings of the Ieee Vlsi Test Symposium. 183-188.  0.393
2000 Mitra S, Saxena NR, McCluskey EJ. Fault escapes in duplex systems Proceedings of the Ieee Vlsi Test Symposium. 453-458.  0.397
1999 Touba NA, McCluskey EJ. RP-SYN: synthesis of random pattern testable circuits with test point insertion Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 18: 1202-1213. DOI: 10.1109/43.775638  0.694
1999 Shirvani PP, McCluskey EJ. PADded cache: a new fault-tolerance technique for cache memories Proceedings of the Ieee Vlsi Test Symposium. 440-445.  0.806
1998 Chang JTY, Tseng CW, Chu YC, Wattal S, Purtell M, McCluskey EJ. Experimental results for IDDQ and VLV testing Proceedings of the Ieee Vlsi Test Symposium. 118-123.  0.48
1998 Chang JTY, Tseng CW, Li CMJ, Purtell M, McCluskey EJ. Analysis of pattern-dependent and timing-dependent failures in an experimental test chip Ieee International Test Conference (Tc). 184-193.  0.432
1997 Touba NA, McCluskey EJ. Logic synthesis of multilevel circuits with concurrent error detection Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 16: 783-789. DOI: 10.1109/43.644041  0.644
1997 Touba NA, McCluskey EJ. Pseudo-random pattern testing of bridging faults Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 54-60.  0.445
1997 Makar SR, McCluskey EJ. ATPG for scan chain latches and flip-flops Proceedings of the Ieee Vlsi Test Symposium. 364-369.  0.378
1997 Makar SR, McCluskey EJ. Iddq test pattern generation for scan chain latches and flip-flops Ieee International Workshop On Iddq Testing, Digest of Papers. 2-6.  0.437
1996 Chang JTY, McCluskey EJ. Quantitative analysis of very-low-voltage testing Proceedings of the Ieee Vlsi Test Symposium. 332-337.  0.313
1996 Norwood RB, McCluskey EJ. Orthogonal scan: Low overhead scan for data paths Ieee International Test Conference (Tc). 659-668.  0.316
1996 Touba NA, McCluskey EJ. Altering a pseudo-random bit sequence for scan-based BIST Ieee International Test Conference (Tc). 167-175.  0.446
1996 Touba NA, McCluskey EJ. Applying two-pattern tests using scan-mapping Proceedings of the Ieee Vlsi Test Symposium. 393-397.  0.378
1996 Touba NA, McCluskey EJ. Test point insertion based on path tracing Proceedings of the Ieee Vlsi Test Symposium. 2-8.  0.418
1996 Franco P, Ma S, Chang J, Chu YC, Wattal S, McCluskey EJ, Stokes RL, Farwell WD. Analysis and detection of timing failures in an experimental test chip Ieee International Test Conference (Tc). 691-700.  0.368
1995 Ma SC, McCluskey EJ. Open Faults in BiCMOS Gates Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 14: 567-575. DOI: 10.1109/43.384417  0.379
1995 Ma SC, Franco P, McCluskey EJ. Experimental chip to evaluate test techniques experiment results Ieee International Test Conference (Tc). 663-672.  0.417
1995 Yamada T, Yamazaki K, McCluskey EJ. Simple technique for locating gate-level faults in combinatorial circuits Proceedings of the Asian Test Symposium. 65-70.  0.415
1995 Touba NA, McCluskey EJ. Synthesis of mapping logic for generating transformed pseudo-random patterns for BIST Ieee International Test Conference (Tc). 674-682.  0.408
1995 Franco P, Farwell WD, Stokes RL, McCluskey EJ. Experimental chip to evaluate test techniques chip and experiment design Ieee International Test Conference (Tc). 653-662.  0.326
1995 Makar SR, McCluskey EJ. Functional tests for scan chain latches Ieee International Test Conference (Tc). 606-615.  0.39
1995 Makar SR, McCluskey EJ. Checking experiments to test latches Proceedings of the Ieee Vlsi Test Symposium. 196-201.  0.447
1993 Avra LJ, McCluskey EJ. Synthesizing for scan dependence in built-in self-testable designs Proceedings of the International Test Conference. 734-743.  0.394
1993 McCluskey EJ. Quality and single-stuck faults Proceedings of the International Test Conference. 597.  0.349
1992 Ma SC, McCluskey EJ. Non-conventional faults in BiCMOS digital circuits Proceedings - International Test Conference. 1992: 882-891. DOI: 10.1109/TEST.1992.527914  0.335
1991 McCluskey EJ. Techniques for test output response analysis Proceedings - Ieee International Symposium On Circuits and Systems. 3: 1869-1872.  0.342
1989 Millman SD, McCluskey EJ. Detecting stuck-open faults with stuck-at test sets Proceedings of the Custom Integrated Circuits Conference. 22.3.1-22.3.4. DOI: 10.1109/CICC.1989.56809  0.439
1989 McCluskey EJ, Buelow F. IC quality and test transparency Ieee Transactions On Industrial Electronics. 36: 197-202. DOI: 10.1109/41.19069  0.335
1988 Wang LT, Mccluskey EJ. Circuits for Pseudoexhaustive Test Pattern Generation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 7: 1068-1080. DOI: 10.1109/43.7806  0.493
1988 Mccluskey EJ, Makar S, Mourad S, Wagner KD. Probability Models for Pseudorandom Test Sequences Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 7: 68-74. DOI: 10.1109/43.3131  0.48
1988 Liu DL, Mccluskey EJ. Design of Large Embedded CMOS PLA's for Built-in Self-Test Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 7: 50-59. DOI: 10.1109/43.3129  0.452
1987 Amer HH, McCluskey EJ. Calculation of Coverage Parameter Ieee Transactions On Reliability. 194-198. DOI: 10.1109/TR.1987.5222338  0.329
1987 Wagner KD, Chin CK, McCluskey EJ. Pseudorandom Testing Ieee Transactions On Computers. 332-343. DOI: 10.1109/TC.1987.1676905  0.512
1987 Chin CK, Mccluskey EJ. Test Length for Pseudorandom Testing Ieee Transactions On Computers. 252-256. DOI: 10.1109/TC.1987.1676892  0.431
1987 Liu DL, McCluskey EJ. CMOS Scan-Path IC Design for Stuck-Open Fault Testability Ieee Journal of Solid-State Circuits. 22: 880-885. DOI: 10.1109/JSSC.1987.1052828  0.469
1987 Mouradd S, Hughes JLA, McCluskey EJ. Effectiveness of single fault tests to detect multiple faults in parity trees Computers and Mathematics With Applications. 13: 455-459. DOI: 10.1016/0898-1221(87)90075-7  0.444
1985 McCluskey EJ. Built-In Self-Test Strutures Ieee Design and Test of Computers. 2: 29-36. DOI: 10.1109/MDT.1985.294857  0.363
1985 McCluskey EJ. Built-In Self-Test Techniques Ieee Design and Test of Computers. 2: 21-28. DOI: 10.1109/MDT.1985.294856  0.375
1985 Mahmood A, Andrews DM, McCluskey EJ. WRITING EXECUTABLE ASSERTIONS TO TEST FLIGHT SOFTWARE Conference Record - Asilomar Conference On Circuits, Systems & Computers. 262-266.  0.334
1985 McCluskey EJ. TESTING SEMI-CUSTOM LOGIC Semiconductor International. 8: 118-123.  0.378
1985 McCluskey EJ. TEST TEACHING Digest of Papers - International Test Conference. 235.  0.373
1984 Lu DJ, Mccluskey EJ. Quantitative Evaluation of Self-Checking Circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 3: 150-155. DOI: 10.1109/TCAD.1984.1270069  0.309
1984 Mccluskey EJ. Verification Testing — A Pseudoexhaustive Test Technique Ieee Transactions On Computers. 541-546. DOI: 10.1109/TC.1984.1676477  0.516
1984 McCluskey EJ. PSEUDO-EXHAUSTIVE TESTING FOR VLSI DEVICES . IV. 5-IV. 21.  0.397
1984 Mahmood A, Andrews DM, McCluskey EJ. EXECUTABLE ASSERTIONS AND FLIGHT SOFTWARE Aiaa Paper. 346-351.  0.367
1983 Xu X, McCluskey EJ. TEST GENERATION AND FAULT DIAGNOSIS FOR MULTIPLE FAULTS IN COMBINATIONAL CIRCUITS Digest of Papers - Ftcs (Fault-Tolerant Computing Symposium). 110-113.  0.41
1983 Mahmood A, McCluskey EJ, Lu DJ. CONCURRENT FAULT DETECTION USING A WATCHDOG PROCESSOR AND ASSERTIONS Digest of Papers - International Test Conference. 622-628.  0.345
1982 Khakbaz J, McCluskey EJ. Concurrent Error Detection and Testing for Large PLA's Ieee Transactions On Electron Devices. 29: 756-764. DOI: 10.1109/T-ED.1982.20774  0.33
1982 McCluskey EJ. TEST QUESTIONS Digest of Papers - Ftcs (Fault-Tolerant Computing Symposium). 43.  0.347
1982 McCluskey EJ. BUILT-IN VERIFICATION TEST Digest of Papers - International Test Conference. 183-190.  0.382
1981 Mccluskey EJ, Bozorgui-Nesbat S. Design for Autonomous Test Ieee Transactions On Computers. 866-875. DOI: 10.1109/Tcs.1981.1084930  0.559
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