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Jay B. Brockman

Affiliations: 
University of Notre Dame, Notre Dame, IN, United States 
Area:
Computer Science
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"Jay Brockman"
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Shyamkumar Thoziyoor grad student 2008 Notre Dame
Shannon K. Kuntz grad student 2009 Notre Dame

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Publications

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Chen K, Li S, Ahn JH, et al. (2015) History-Assisted Adaptive-Granularity Caches (HAAG$) for high performance 3D DRAM architectures Proceedings of the International Conference On Supercomputing. 2015: 251-261
Li S, Ahn JH, Strong RD, et al. (2013) The McPAT framework for multicore and manycore architectures: Simultaneously modeling power, area, and timing Transactions On Architecture and Code Optimization. 10
Li S, Chen K, Hsieh MY, et al. (2012) System implications of memory reliability in exascale computing Hp Laboratories Technical Report
Karda K, Sutar S, Brockman JB, et al. (2012) Bistable-body tunnel SRAM Ieee Transactions On Nanotechnology. 11: 1067-1072
Li S, Yoon DH, Chen K, et al. (2012) MAGE: Adaptive granularity and ECC for resilient and power efficient memory systems International Conference For High Performance Computing, Networking, Storage and Analysis, Sc
Chen K, Li S, Muralimanohar N, et al. (2012) CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory Proceedings -Design, Automation and Test in Europe, Date. 33-38
Li S, Kuntz S, Brockman JB, et al. (2011) Lightweight Chip Multi-Threading (LCMT): Maximizing Fine-Grained Parallelism On-Chip Ieee Transactions On Parallel and Distributed Systems. 22: 1178-1191
Li S, Ahn JH, Strong RD, et al. (2009) McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures Proceedings of the Annual International Symposium On Microarchitecture, Micro. 469-480
Thoziyoor S, Ahn JH, Monchiero M, et al. (2008) A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies Acm Sigarch Computer Architecture News. 36: 51-62
Thoziyoor S, Ahn JH, Monchiero M, et al. (2008) A comprehensive memory modeling tool and its application to the design and analysis of future memory hierarchies Proceedings - International Symposium On Computer Architecture. 51-62
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