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Changhwan Shin, Ph.D. - Publications

Affiliations: 
2011 Electrical Engineering & Computer Sciences University of California, Berkeley, Berkeley, CA, United States 
Area:
Nanofabrication
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113 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2022 Noh C, Han C, Won SM, Shin C. Vertical Gate-All-Around Device Architecture to Improve the Device Performance for Sub-5-nm Technology. Micromachines. 13. PMID 36144174 DOI: 10.3390/mi13091551  0.39
2022 Sun M, Baac HW, Shin C. Simulation Study: The Impact of Structural Variations on the Characteristics of a Buried-Channel-Array Transistor (BCAT) in DRAM. Micromachines. 13. PMID 36144099 DOI: 10.3390/mi13091476  0.395
2021 Park J, Jang W, Shin C. Gate-Stack Engineering to Improve the Performance of 28 nm Low-Power High-K/Metal-Gate Device. Micromachines. 12. PMID 34442508 DOI: 10.3390/mi12080886  0.361
2020 Yoon C, Moon S, Shin C. Study of a hysteresis window of FinFET and fully-depleted silicon-on-insulator (FDSOI) MOSFET with ferroelectric capacitor. Nano Convergence. 7: 19. PMID 32483648 DOI: 10.1186/S40580-020-00230-X  0.376
2020 Choi Y, Shin J, Moon S, Shin C. Investigation on Threshold Voltage Adjustment of Threshold Switching Devices with HfO/AlO Superlattice on Transparent ITO/Glass Substrate. Micromachines. 11. PMID 32455725 DOI: 10.3390/Mi11050525  0.432
2020 Park J, Kim J, Showdhury S, Shin C, Rhee H, Yeo MS, Cho E, Yi J. Electrical Characteristics of Bulk FinFET According to Spacer Length Electronics. 9: 1283. DOI: 10.3390/Electronics9081283  0.421
2020 Yoon C, Shin C. Electrical Characteristics of Nanoelectromechanical Relay with Multi-Domain HfO2-Based Ferroelectric Materials Electronics. 9: 1208. DOI: 10.3390/Electronics9081208  0.339
2020 Moon S, Shin J, Shin C. Understanding of Polarization-Induced Threshold Voltage Shift in Ferroelectric-Gated Field Effect Transistor for Neuromorphic Applications Electronics. 9: 704. DOI: 10.3390/Electronics9050704  0.436
2020 Lee C, Sung J, Shin C. Understanding of Feedback Field-Effect Transistor and Its Applications Applied Sciences. 10: 3070. DOI: 10.3390/App10093070  0.306
2020 Lee C, Shin C. Study on Various Device Structures for Steep-Switching Silicon-on-Insulator Feedback Field-Effect Transistors Ieee Transactions On Electron Devices. 67: 1852-1858. DOI: 10.1109/Ted.2020.2975007  0.508
2020 Yoon C, Min J, Shin J, Shin C. Device Design Guideline for HfO₂-Based Ferroelectric-Gated Nanoelectromechanical System Ieee Journal of the Electron Devices Society. 8: 608-613. DOI: 10.1109/Jeds.2020.3001272  0.406
2020 Hong Y, Choi Y, Shin C. NCFET-Based 6-T SRAM: Yield Estimation Based on Variation-Aware Sensitivity Ieee Journal of the Electron Devices Society. 8: 182-188. DOI: 10.1109/Jeds.2020.2973966  0.357
2020 Seo J, Shin C. Experimental study of interface traps in MOS capacitor with Al-doped HfO2 Semiconductor Science and Technology. 35: 85029. DOI: 10.1088/1361-6641/Ab9847  0.333
2020 Jung T, Shin C. Device-design optimization of ferroelectric-gated vertical tunnel field-effect transistor to suppress ambipolar current Semiconductor Science and Technology. 35: 85010. DOI: 10.1088/1361-6641/Ab8E63  0.453
2020 Choi Y, Hong Y, Ko E, Shin C. Optimization of double metal-gate InAs/Si heterojunction nanowire TFET Semiconductor Science and Technology. 35: 75024. DOI: 10.1088/1361-6641/Ab8B1F  0.342
2020 Wang CW, Ku H, Chiu CY, De S, Qiu BH, Shin C, Lu D. Compact model for PZT ferroelectric capacitors with voltage dependent switching behavior Semiconductor Science and Technology. 35: 55033. DOI: 10.1088/1361-6641/Ab7C79  0.385
2020 Park J, Shin C. Study of random dopant fluctuation in PNPN feedback FET Semiconductor Science and Technology. 35: 35019. DOI: 10.1088/1361-6641/Ab7146  0.449
2020 Choi Y, Hong Y, Shin C. Device design guideline for junctionless gate-all-around nanowire negative-capacitance FET with HfO2-based ferroelectric gate stack Semiconductor Science and Technology. 35: 15011. DOI: 10.1088/1361-6641/Ab5775  0.488
2020 Min J, Shin C. Study of Line Edge Roughness on Various Types of Gate-All-Around Field Effect Transistor Semiconductor Science and Technology. 35: 15004. DOI: 10.1088/1361-6641/Ab52E4  0.369
2020 Yoon C, Shin C. Time-resolved electrical characteristics of ferroelectric-gated fully depleted silicon on insulator devices Solid-State Electronics. 164: 107698. DOI: 10.1016/J.Sse.2019.107698  0.445
2020 Choe K, Park J, Shin C. Theoretical study of ferroelectric-gated nanoelectromechanical diode nonvolatile memory cell Solid-State Electronics. 163: 107662. DOI: 10.1016/J.Sse.2019.107662  0.323
2020 Min J, Choe G, Shin C. Gate-induced drain leakage (GIDL) in MFMIS and MFIS negative capacitance FinFETs Current Applied Physics. 20: 1222-1225. DOI: 10.1016/J.Cap.2020.08.008  0.401
2019 Kim J, Heo K, Kang DH, Shin C, Lee S, Yu HY, Park JH. Rhenium Diselenide (ReSe) Near-Infrared Photodetector: Performance Enhancement by Selective p-Doping Technique. Advanced Science (Weinheim, Baden-Wurttemberg, Germany). 6: 1901255. PMID 31728284 DOI: 10.1002/Advs.201901255  0.34
2019 Oh C, Tewari A, Kim K, Ulayil SK, Shin C, Ahn M, Jeon S. Comprehensive study of high pressure annealing on the ferroelectric properties of Hf0.5Zr0.5O2 thin films. Nanotechnology. PMID 31426039 DOI: 10.1088/1361-6528/Ab3C8F  0.363
2019 Shim J, Jang SW, Lim JH, Kim H, Kang DH, Kim KH, Seo S, Heo K, Shin C, Yu HY, Lee S, Ko DH, Park JH. Polarity control in a single transition metal dichalcogenide (TMD) transistor for homogeneous complementary logic circuits. Nanoscale. PMID 31243409 DOI: 10.1039/C9Nr03441B  0.471
2019 Ko E, Shin J, Shin C. Steep Slope Silicon-on-Insulator Field Effect Transistor with Negative Capacitance: Analysis on Hysteresis. Journal of Nanoscience and Nanotechnology. 19: 6128-6130. PMID 31026921 DOI: 10.1166/Jnn.2019.16990  0.448
2019 Park J, Shin C. Process-Induced Random Variation: Work-Function Variation in Stacked Nanowire Field Effect Transistor. Journal of Nanoscience and Nanotechnology. 19: 6091-6094. PMID 31026914 DOI: 10.1166/Jnn.2019.16993  0.474
2019 Cho H, Shin J, Shin C. Impact of Ferroelectric Capacitor's Electrode Area on the Performance of Negative Capacitance Field Effect Transistor. Journal of Nanoscience and Nanotechnology. 19: 6087-6090. PMID 31026913 DOI: 10.1166/Jnn.2019.16991  0.464
2019 Choe K, Shin C. Ferroelectric-Gated Nanoelectromechanical Nonvolatile Memory Cell Ieee Transactions On Electron Devices. 66: 407-412. DOI: 10.1109/Ted.2018.2881201  0.345
2019 Lee C, Ko E, Shin C. Steep Slope Silicon-On-Insulator Feedback Field-Effect Transistor: Design and Performance Analysis Ieee Transactions On Electron Devices. 66: 286-291. DOI: 10.1109/Ted.2018.2879653  0.486
2019 Yoon JS, Tewari A, Shin C, Jeon S. Influence of High-Pressure Annealing on Memory Properties of Hf 0.5 Zr 0.5 O 2 Based 1T-FeRAM Ieee Electron Device Letters. 40: 1076-1079. DOI: 10.1109/Led.2019.2918797  0.365
2019 Park J, Shin C. Tunnel Field-Effect Transistor With Segmented Channel Ieee Journal of the Electron Devices Society. 7: 621-625. DOI: 10.1109/Jeds.2019.2919331  0.448
2019 Shin J, Shin C. External Resistor-Free Gate Configuration Phase Transition FDSOI MOSFET Ieee Journal of the Electron Devices Society. 7: 186-190. DOI: 10.1109/Jeds.2018.2888888  0.465
2019 Park J, Shin C. Study of work-function variation in stacked multiple-channel-structure device Semiconductor Science and Technology. 34: 125003. DOI: 10.1088/1361-6641/Ab4B7D  0.395
2019 Shin C. Experimental understanding of polarization switching in PZT ferroelectric capacitor Semiconductor Science and Technology. 34: 75004. DOI: 10.1088/1361-6641/Ab1D2E  0.351
2019 Shin J, Shin C. DIBL improvement in hysteresis-free and ferroelectric-gated FinFETs Semiconductor Science and Technology. 34: 65001. DOI: 10.1088/1361-6641/Ab13Fc  0.382
2019 Cho H, Shin C. DIBL enhancement in ferroelectric-gated FinFET Semiconductor Science and Technology. 34: 25004. DOI: 10.1088/1361-6641/Aaf518  0.458
2019 Shin J, Shin C. Experimental observation of zero DIBL in short-channel hysteresis-free ferroelectric-gated FinFET Solid-State Electronics. 153: 12-15. DOI: 10.1016/J.Sse.2018.12.012  0.476
2019 Shin S, Koh CW, Vincent P, Goo JS, Bae J, Lee J, Shin C, Kim H, Woo HY, Shim JW. Ultra-thick semi-crystalline photoactive donor polymer for efficient indoor organic photovoltaics Nano Energy. 58: 466-475. DOI: 10.1016/J.Nanoen.2019.01.061  0.373
2019 Choi H, Park J, Shim JW, Shin C. Negative quantum capacitance effect from Bi2Te1.5Se1.5 with frequency dependent capacitance of polyvinyl alcohol (PVA) film in MOS structure Applied Surface Science. 463: 1046-1050. DOI: 10.1016/J.Apsusc.2018.09.051  0.422
2019 Choi H, Shin C. Negative Capacitance Transistor with Two‐Dimensional Channel Material (Molybdenum disulfide, MoS2) Physica Status Solidi (a). 216: 1900177. DOI: 10.1002/Pssa.201900177  0.37
2018 Cho K, Shin C. Simulation Techniques for Nanoelectromechanical (NEM) Relay. Journal of Nanoscience and Nanotechnology. 18: 6615-6618. PMID 29677845 DOI: 10.1166/Jnn.2018.15701  0.416
2018 Ko E, Shin J, Shin C. Steep switching devices for low power applications: negative differential capacitance/resistance field effect transistors. Nano Convergence. 5: 2. PMID 29399434 DOI: 10.1186/S40580-018-0135-4  0.422
2018 Nam H, Shin C, Park J. Impact of the Metal-Gate Material Properties in FinFET (Versus FD-SOI MOSFET) on High- $\kappa$ /Metal-Gate Work-Function Variation Ieee Transactions On Electron Devices. 65: 4780-4785. DOI: 10.1109/Ted.2018.2872586  0.444
2018 Shin J, Ko E, Shin C. Analysis on the Operation of Negative Differential Resistance FinFET With Pb(Zr 0.52 Ti 0.48 )O 3 Threshold Selector Ieee Transactions On Electron Devices. 65: 19-22. DOI: 10.1109/Ted.2017.2773042  0.426
2018 Shin J, Ko E, Park J, Kim SG, Lee JW, Yu H, Shin C. Super steep-switching (SS ≈ 2 mV/decade) phase-FinFET with Pb(Zr0.52Ti0.48)O3 threshold switching device Applied Physics Letters. 113: 102104. DOI: 10.1063/1.5030966  0.413
2017 Kim GS, Kim SH, Lee TI, Cho BJ, Choi C, Shin C, Shim JH, Kim J, Yu HY. Fermi-Level Unpinning Technique with Excellent Thermal Stability for n-type Germanium. Acs Applied Materials & Interfaces. PMID 28952716 DOI: 10.1021/Acsami.7B10346  0.31
2017 Yeom SW, You B, Cho K, Jung HY, Park J, Shin C, Ju BK, Kim JW. Silver Nanowire/Colorless-Polyimide Composite Electrode: Application in Flexible and Transparent Resistive Switching Memory. Scientific Reports. 7: 3438. PMID 28611411 DOI: 10.1038/S41598-017-03746-1  0.305
2017 Choi H, Shin J, Shin C. Impact of Source/Drain Metal Work Function on the Electrical Characteristics of Anatase TiO2-Based Thin Film Transistors Ecs Journal of Solid State Science and Technology. 6: 379. DOI: 10.1149/2.0121707Jss  0.42
2017 Jo J, Kim MG, Lee H, Choi H, Shin C. Transconductance Amplification by the Negative Capacitance in Ferroelectric-Gated P3HT Thin-Film Transistor Ieee Transactions On Electron Devices. 64: 4974-4979. DOI: 10.1109/Ted.2017.2764508  0.438
2017 Choe K, Shin C. Adjusting the Operating Voltage of an Nanoelectromechanical Relay Using Negative Capacitance Ieee Transactions On Electron Devices. 64: 5270-5273. DOI: 10.1109/Ted.2017.2756676  0.448
2017 Park J, Shin C. Impact of Interface Traps and Surface Roughness on the Device Performance of Stacked-Nanowire FETs Ieee Transactions On Electron Devices. 64: 4025-4030. DOI: 10.1109/Ted.2017.2741979  0.389
2017 Lee Y, Shin C. Impact of Equivalent Oxide Thickness on Threshold Voltage Variation Induced by Work-Function Variation in Multigate Devices Ieee Transactions On Electron Devices. 64: 2452-2456. DOI: 10.1109/Ted.2017.2673859  0.46
2017 Lee H, Yoon Y, Shin C. Current-Voltage Model for Negative Capacitance Field-Effect Transistors Ieee Electron Device Letters. 38: 669-672. DOI: 10.1109/Led.2017.2679102  0.46
2017 Ko E, Lee JW, Shin C. Negative Capacitance FinFET With Sub-20-mV/decade Subthreshold Slope and Minimal Hysteresis of 0.48 V Ieee Electron Device Letters. 38: 418-421. DOI: 10.1109/Led.2017.2672967  0.408
2017 Ko E, Lee H, Goh Y, Jeon S, Shin C. Sub-60-mV/decade Negative Capacitance FinFET With Sub-10-nm Hafnium-Based Ferroelectric Capacitor Ieee Journal of the Electron Devices Society. 5: 306-309. DOI: 10.1109/Jeds.2017.2731401  0.482
2017 Ku H, Shin C. Transient Response of Negative Capacitance in P(VDF 0.75 -TrFE 0.25 ) Organic Ferroelectric Capacitor Ieee Journal of the Electron Devices Society. 5: 232-236. DOI: 10.1109/Jeds.2017.2670546  0.329
2017 Ko E, Shin C. Effective drive current in steep slope FinFET (vs. conventional FinFET) Applied Physics Letters. 111: 152105. DOI: 10.1063/1.4998508  0.481
2017 Hong SB, Park JH, Lee TH, Lim JH, Shin C, Park YW, Kim TG. Variation of poly-Si grain structures under thermal annealing and its effect on the performance of TiN/Al2O3/Si3N4/SiO2/poly-Si capacitors Applied Surface Science. 477: 104-110. DOI: 10.1016/J.Apsusc.2017.11.226  0.35
2017 Choi H, Kim TG, Shin C. Measurement of the quantum capacitance from two-dimensional surface state of a topological insulator at room temperature Applied Surface Science. 407: 16-20. DOI: 10.1016/J.Apsusc.2017.02.090  0.401
2016 Kim GS, Kim SW, Kim SH, Park J, Seo Y, Cho BJ, Shin C, Shim JH, Yu HY. Effective Schottky Barrier Height Lowering of Metal/n-Ge with a TiO2/GeO2 Interlayer Stack. Acs Applied Materials & Interfaces. PMID 27977113 DOI: 10.1021/Acsami.6B10947  0.384
2016 Lee H, Cho K, Shin C, Shin H. Impact of Trap Position on Random Telegraph Noise in a 70-Å Nanowire Field-Effect Transistor Journal of Semiconductor Technology and Science. 16: 185-190. DOI: 10.5573/Jsts.2016.16.2.185  0.44
2016 Ko E, Lee H, Park J, Shin C. Vertical Tunnel FET: Design Optimization With Triple Metal-Gate Layers Ieee Transactions On Electron Devices. 63: 5030-5035. DOI: 10.1109/Ted.2016.2619372  0.507
2016 Park J, Lee H, Oh S, Shin C. Design for Variation-Immunity in Sub-10-nm Stacked-Nanowire FETs to Suppress LER-induced Random Variations Ieee Transactions On Electron Devices. 63: 5048-5054. DOI: 10.1109/Ted.2016.2615868  0.36
2016 Oh S, Shin C. 3-D Quasi-Atomistic Model for Line Edge Roughness in Nonplanar MOSFETs Ieee Transactions On Electron Devices. 63: 4617-4623. DOI: 10.1109/Ted.2016.2614490  0.437
2016 Shin C, Kim JK, Kim GS, Lee H, Cho BJ, Yu HY. Random Dopant Fluctuation-Induced Threshold Voltage Variation-Immune Ge FinFET With Metal-Interlayer-Semiconductor Source/Drain Ieee Transactions On Electron Devices. DOI: 10.1109/Ted.2016.2606511  0.406
2016 Nam H, Lee Y, Park J, Shin C. Study of Work-Function Variation in High- $\kappa $ /Metal-Gate Gate-All-Around Nanowire MOSFET Ieee Transactions On Electron Devices. 63: 3338-3341. DOI: 10.1109/Ted.2016.2574328  0.389
2016 Lee H, Park JD, Shin C. Study of Random Variation in Germanium-Source Vertical Tunnel FET Ieee Transactions On Electron Devices. DOI: 10.1109/Ted.2016.2539209  0.43
2016 Lee H, Park J, Shin C. Performance Booster for Vertical Tunnel Field-Effect Transistor: Field-Enhanced High- $\kappa $ Layer Ieee Electron Device Letters. 37: 1383-1386. DOI: 10.1109/Led.2016.2606660  0.41
2016 Kim GS, Yoo G, Seo Y, Kim SH, Cho K, Cho BJ, Shin C, Park JH, Yu HY. Effect of Hydrogen Annealing on Contact Resistance Reduction of Metal-Interlayer-n-Germanium Source/Drain Structure Ieee Electron Device Letters. 37: 709-712. DOI: 10.1109/Led.2016.2558582  0.37
2016 Ahn J, Kim JK, Kim SW, Kim GS, Shin C, Cho BJ, Yu HY. Effect of Metal Nitride on Contact Resistivity of Metal-Interlayer-Ge Source/Drain in Sub-10-nm n-Type Ge FinFET Ieee Electron Device Letters. 37: 705-708. DOI: 10.1109/Led.2016.2553132  0.344
2016 Jo J, Shin C. Negative capacitance field effect transistor with hysteresis-free sub-60-mV/decade switching Ieee Electron Device Letters. 37: 245-248. DOI: 10.1109/Led.2016.2523681  0.456
2016 Choi H, Lee H, Park J, Yu H, Kim TG, Shin C. Experimental evidence of negative quantum capacitance in topological insulator for sub-60-mV/decade steep switching device Applied Physics Letters. 109: 203505. DOI: 10.1063/1.4968183  0.41
2016 Shin C, Kim JK, Yu HY. Threshold voltage variation-immune FinFET design with metal-interlayer-semiconductor source/drain structure Current Applied Physics. 16: 618-622. DOI: 10.1016/J.Cap.2016.03.006  0.418
2015 Jo J, Choi WY, Park JD, Shim JW, Yu HY, Shin C. Negative Capacitance in Organic/Ferroelectric Capacitor to Implement Steep Switching MOS Devices. Nano Letters. 15: 4553-6. PMID 26103511 DOI: 10.1021/Acs.Nanolett.5B01130  0.483
2015 Jung H, Chae SY, Shin C, Min BK, Joo OS, Hwang YJ. Effect of the Si/TiO2/BiVO4 heterojunction on the onset potential of photocurrents for solar water oxidation. Acs Applied Materials & Interfaces. 7: 5788-96. PMID 25720751 DOI: 10.1021/Am5086484  0.314
2015 Oh S, Shin C, Kwon W. A compact effective-current model for power performance analysis on state-of-the-art technology development and benchmarking Japanese Journal of Applied Physics. 54: 124302. DOI: 10.7567/Jjap.54.124302  0.385
2015 Oh S, Jo J, Lee H, Lee GS, Park JD, Shin C. Worst case sampling method with confidence ellipse for estimating the impact of random variation on static random access memory (SRAM) Journal of Semiconductor Technology and Science. 15: 374-380. DOI: 10.5573/Jsts.2015.15.3.374  0.302
2015 Kwon W, Park IJ, Shin C. Highly Scalable NAND Flash Memory Cell Design Embracing Backside Charge Storage Journal of Semiconductor Technology and Science. 15: 286-291. DOI: 10.5573/Jsts.2015.15.2.286  0.378
2015 Park S, Lee JH, Shin C. Impact of the double-patterning technique on the LER-induced threshold voltage variation in symmetric tunnel field-effect transistor Ieice Electronics Express. 12: 20150349-20150349. DOI: 10.1587/Elex.12.20150349  0.385
2015 Lee Y, Nam H, Park JD, Shin C. Study of work-function variation for high-κ/metal-gate Ge-source tunnel field-effect transistors Ieee Transactions On Electron Devices. 62: 2143-2147. DOI: 10.1109/Ted.2015.2436815  0.463
2015 Lee H, Park S, Lee Y, Nam H, Shin C. Random Variation Analysis and Variation-Aware Design of Symmetric Tunnel Field-Effect Transistor Ieee Transactions On Electron Devices. 62: 1778-1783. DOI: 10.1109/Ted.2014.2365805  0.464
2015 Lee GS, Shin C. Worst case sampling method to estimate the impact of random variation on static random access memory Ieee Transactions On Electron Devices. 62: 1705-1709. DOI: 10.1109/Ted.2014.2361913  0.342
2015 Kim SH, Kim GS, Kim JK, Park JH, Shin C, Choi C, Yu HY. Fermi-Level Unpinning Using a Ge-Passivated Metal-Interlayer-Semiconductor Structure for Non-Alloyed Ohmic Contact of High-Electron-Mobility Transistors Ieee Electron Device Letters. 36: 884-886. DOI: 10.1109/Led.2015.2453479  0.385
2015 Kim GS, Kim SH, Kim JK, Shin C, Park JH, Saraswat KC, Cho BJ, Yu HY. Surface Passivation of Germanium Using SF6 Plasma to Reduce Source/Drain Contact Resistance in Germanium n-FET Ieee Electron Device Letters. 36: 745-747. DOI: 10.1109/Led.2015.2440434  0.505
2015 Jo J, Shin C. Impact of temperature on negative capacitance field-effect transistor Electronics Letters. 51: 106-108. DOI: 10.1049/El.2014.3515  0.403
2015 Jo J, Shin C. Experimental observation of voltage amplification using negative capacitance for sub-60 mV/decade CMOS devices Current Applied Physics. 15: 352-355. DOI: 10.1016/J.Cap.2014.12.029  0.471
2015 Nam H, Cho MH, Shin C. Symmetric tunnel field-effect transistor (S-TFET) Current Applied Physics. 15: 71-77. DOI: 10.1016/J.Cap.2014.11.006  0.471
2014 Nam H, Park S, Shin C. Performance and Variation-Immunity Benefits of Segmented-Channel MOSFETs (SegFETs) Using HfO 2 or SiO 2 Trench Isolation Journal of Semiconductor Technology and Science. 14: 427-435. DOI: 10.5573/Jsts.2014.14.4.427  0.318
2014 Shin C. Assistive circuit for lowering minimum operating voltage and balancing read/write margins in an SRAM array Journal of Semiconductor Technology and Science. 14: 184-188. DOI: 10.5573/Jsts.2014.14.2.184  0.365
2014 Lee GS, Shin C. Computing-inexpensive matrix model for estimating the threshold voltage variation by workfunction variation in high-κ/metal-gate MOSFETs Journal of Semiconductor Technology and Science. 14: 96-99. DOI: 10.5573/Jsts.2014.14.1.096  0.387
2014 Nam H, Lee GS, Lee H, Park IJ, Shin C. Analysis of Random Variations and Variation-Robust Advanced Device Structures Journal of Semiconductor Technology and Science. 14: 8-22. DOI: 10.5573/Jsts.2014.14.1.008  0.444
2014 Shin C. State-of-the-art silicon device miniaturization technology and its challenges Ieice Electronics Express. 11. DOI: 10.1587/Elex.11.20142005  0.388
2014 Shin C, Lee GG, Han DH, Han SP, Tokumitsu E, Ohmi SI, Kim DJ, Ishiwara H, Park M, Kim SH, Lee WG, Hwang YJ, Park BE. Experimental demonstration of a ferroelectric FET using paper substrate Ieice Electronics Express. 11. DOI: 10.1587/Elex.11.20140447  0.436
2014 Park IJ, Jeon SG, Shin C. A new slit-type vacuum-channel transistor Ieee Transactions On Electron Devices. 61: 4186-4191. DOI: 10.1109/Ted.2014.2361912  0.463
2014 Nam H, Shin C. Impact of current flow shape in tapered (versus rectangular) FinFET on threshold voltage variation induced by work-function variation Ieee Transactions On Electron Devices. 61: 2007-2011. DOI: 10.1109/Ted.2014.2318696  0.395
2014 Kim JK, Kim GS, Nam H, Shin C, Park JH, Cho BJ, Saraswat KC, Yu HY. The efficacy of metal-interfacial layer-semiconductor source/drain structure on sub-10-nm n-type ge FinFET performances Ieee Electron Device Letters. 35: 1185-1187. DOI: 10.1109/Led.2014.2364574  0.519
2014 Kim GS, Kim JK, Kim SH, Jo J, Shin C, Park JH, Saraswat KC, Yu HY. Specific contact resistivity reduction through Ar plasma-treated TiO2-x interfacial layer to metal/Ge contact Ieee Electron Device Letters. 35: 1076-1078. DOI: 10.1109/Led.2014.2354679  0.503
2014 Kim JK, Kim GS, Shin C, Park JH, Saraswat KC, Yu HY. Analytical study of interfacial layer doping effect on contact resistivity in metal-interfacial layer-Ge structure Ieee Electron Device Letters. 35: 705-707. DOI: 10.1109/Led.2014.2323256  0.526
2013 Park IJ, Shin C. Monte Carlo Simulation Study: the effects of double- patterning versus single-patterning on the line-edge- roughness (LER) in FDSOI Tri-gate MOSFETs Journal of Semiconductor Technology and Science. 13: 511-515. DOI: 10.5573/Jsts.2013.13.5.511  0.384
2013 Park IJ, Shin C. Effect of double-patterning and double-etching on the line-edge-roughness of multi-gate bulk MOSFETs Ieice Electronics Express. 10: 20130108-20130108. DOI: 10.1587/Elex.10.20130108  0.321
2013 Damrongplasit N, Kim SH, Shin C, Liu TK. Impact of Gate Line-Edge Roughness (LER) Versus Random Dopant Fluctuations (RDF) on Germanium-Source Tunnel FET Performance Ieee Transactions On Nanotechnology. 12: 1061-1067. DOI: 10.1109/Tnano.2013.2278153  0.456
2013 Ho B, Sun X, Shin C, Liu TK. Design Optimization of Multigate Bulk MOSFETs Ieee Transactions On Electron Devices. 60: 28-33. DOI: 10.1109/Ted.2012.2224870  0.678
2013 Nam H, Shin C. Study of high-k/metal-gate work function variation in FinFET: The modified RGG concept Ieee Electron Device Letters. 34: 1560-1562. DOI: 10.1109/Led.2013.2287283  0.432
2013 Shin C, Park IJ. Impact of Using Double-Patterning Versus Single-Patterning on Threshold Voltage $(V_{\rm TH})$ Variation in Quasi-Planar Tri-Gate Bulk MOSFETs Ieee Electron Device Letters. 34: 578-580. DOI: 10.1109/Led.2013.2249653  0.41
2013 Nam H, Shin C. Study of high-k/metal-gate work-function variation using rayleigh distribution Ieee Electron Device Letters. 34: 532-534. DOI: 10.1109/Led.2013.2247376  0.384
2011 Damrongplasit N, Shin C, Kim SH, Vega RA, King Liu TJ. Study of random dopant fluctuation effects in Germanium-source tunnel FETs Ieee Transactions On Electron Devices. 58: 3541-3548. DOI: 10.1109/Ted.2011.2161990  0.744
2011 Sun X, Moroz V, Damrongplasit N, Shin C, Liu TJK. Variation study of the planar ground-plane bulk MOSFET, SOI FinFET, and trigate bulk MOSFET designs Ieee Transactions On Electron Devices. 58: 3294-3299. DOI: 10.1109/Ted.2011.2161479  0.508
2011 Shin C, Damrongplasit N, Sun X, Tsukamoto Y, Nikolic B, Liu TJK. Performance and yield benefits of quasi-planar bulk CMOS technology for 6-T SRAM at the 22-nm node Ieee Transactions On Electron Devices. 58: 1846-1854. DOI: 10.1109/Ted.2011.2139213  0.512
2011 Shin C, Tsai CH, Wu MH, Chang CF, Liu YR, Kao CY, Lin GS, Chiu KL, Fu CS, Tsai CT, Liang CW, Nikolić B, Liu TJK. Quasi-planar bulk CMOS technology for improved SRAM scalability Solid-State Electronics. 65: 184-190. DOI: 10.1016/J.Sse.2011.06.022  0.391
2010 Shin C, Cho MH, Tsukamoto Y, Nguyen B, Mazuré C, Nikolić B, Liu TK. Performance and Area Scaling Benefits of FD-SOI Technology for 6-T SRAM Cells at the 22-nm Node Ieee Transactions On Electron Devices. 57: 1301-1309. DOI: 10.1109/Ted.2010.2046070  0.425
2009 Shin C, Sun X, Liu TK. Study of Random-Dopant-Fluctuation (RDF) Effects for the Trigate Bulk MOSFET Ieee Transactions On Electron Devices. 56: 1538-1542. DOI: 10.1109/Ted.2009.2020321  0.565
2008 Sun X, Lu Q, Moroz V, Takeuchi H, Gebara G, Wetzel J, Ikeda S, Shin C, King Liu TJ. Tri-gate bulk MOSFET design for CMOS scaling to the end of the roadmap Ieee Electron Device Letters. 29: 491-493. DOI: 10.1109/Led.2008.919795  0.751
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