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Sriramkumar Venugopalan, Ph.D. - Publications

Affiliations: 
2013 Electrical Engineering & Computer Sciences University of California, Berkeley, Berkeley, CA, United States 
Area:
Semiconductor Device Technologies
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16 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2014 Chauhan YS, Venugopalan S, Chalkiadaki MA, Karim MAU, Agarwal H, Khandelwal S, Paydavosi N, Duarte JP, Enz CC, Niknejad AM, Hu C. BSIM6: Analog and RF compact model for bulk MOSFET Ieee Transactions On Electron Devices. 61: 234-244. DOI: 10.1109/Ted.2013.2283084  0.479
2013 Venugopalan S, Karim MA, Salahuddin S, Niknejad AM, Hu CC. Phenomenological compact model for QM charge centroid in multigate FETs Ieee Transactions On Electron Devices. 60: 1480-1484. DOI: 10.1109/Ted.2013.2245419  0.386
2013 Duarte JP, Paydavosi N, Venugopalan S, Sachid A, Hu C. Unified FinFET compact model: Modelling trapezoidal triple-gate FinFETs International Conference On Simulation of Semiconductor Processes and Devices, Sispad. 135-138. DOI: 10.1109/SISPAD.2013.6650593  0.356
2013 Agarwal H, Venugopalan S, Chalkiadaki MA, Paydavosi N, Duarte JP, Agnihotri S, Yadav C, Kushwaha P, Chauhan YS, Enz CC, Niknejad A, Hu C. Recent enhancements in BSIM6 bulk MOSFET model International Conference On Simulation of Semiconductor Processes and Devices, Sispad. 53-56. DOI: 10.1109/SISPAD.2013.6650572  0.346
2013 Paydavosi N, Venugopalan S, Chauhan YS, Duarte JP, Jandhyala S, Niknejad AM, Hu CC. BSIM - SPICE models enable FinFET and UTB IC designs Ieee Access. 1: 201-215. DOI: 10.1109/Access.2013.2260816  0.437
2013 Chauhan YS, Venugopalan S, Paydavosi N, Kushwaha P, Jandhyala S, Duarte JP, Agnihotri S, Yadav C, Agarwal H, Niknejad A, Hu CC. BSIM compact MOSFET models for SPICE simulation Proceedings of the 20th International Conference On Mixed Design of Integrated Circuits and Systems, Mixdes 2013. 23-28.  0.395
2012 Khandelwal S, Chauhan YS, Lu DD, Venugopalan S, Ahosan Ul Karim M, Sachid AB, Nguyen BY, Rozeau O, Faynot O, Niknejad AM, Hu CC. BSIM-IMG: A compact model for ultrathin-body SOI MOSFETs with back-gate control Ieee Transactions On Electron Devices. 59: 2019-2026. DOI: 10.1109/Ted.2012.2198065  0.416
2012 Karim MA, Chauhan YS, Venugopalan S, Sachid AB, Lu DD, Nguyen BY, Faynot O, Niknejad AM, Hu C. Extraction of isothermal condition and thermal network in UTBB SOI MOSFETs Ieee Electron Device Letters. 33: 1306-1308. DOI: 10.1109/Led.2012.2205659  0.361
2012 Khandelwal S, Chauhan YS, Karim MA, Venugopalan S, Sachid A, Niknejad A, Hu C. Analysis and modeling of vertical non-uniform doping in bulk MOSFETs for circuit simulation 2012 8th International Caribbean Conference On Devices, Circuits and Systems, Iccdcs 2012. DOI: 10.1109/ICCDCS.2012.6188935  0.33
2012 Chalkiadaki MA, Mangia A, Enz CC, Chauhan YS, Karim MA, Venugopalan S, Niknejad A, Hu C. Evaluation of the BSIM6 compact MOSFET model's scalability in 40nm CMOS technology European Solid-State Circuits Conference. 34-37. DOI: 10.1109/ESSCIRC.2012.6341250  0.311
2012 Chauhan YS, Venugopalan S, Karim MA, Khandelwal S, Paydavosi N, Thakur P, Niknejad AM, Hu CC. BSIM Industry standard compact MOSFET models European Solid-State Circuits Conference. 30-33. DOI: 10.1109/ESSCIRC.2012.6341249  0.355
2012 Venugopalan S, Lu DD, Kawakami Y, Lee PM, Niknejad AM, Hu C. BSIM-CG: A compact model of cylindrical/surround gate MOSFET for circuit simulations Solid-State Electronics. 67: 79-89. DOI: 10.1016/J.Sse.2011.09.001  0.477
2012 Chauhan YS, Karim MA, Venugopalan S, Khandelwal S, Thakur P, Paydavosi N, Sachid AB, Niknejad A, Hu C. BSIM6: Symmetric bulk MOSFET model Technical Proceedings of the 2012 Nsti Nanotechnology Conference and Expo, Nsti-Nanotech 2012. 724-729.  0.323
2011 Venugopalan S, Chauhan YS, Lu DD, Karim MA, Niknejad AM, Hu C. Modeling intrinsic and extrinsic asymmetry of 3D cylindrical gate/gate-all-around FETs for circuit simulations 2011 11th Annual Non-Volatile Memory Technology Symposium, Nvmts 2011. 125-128. DOI: 10.1109/NVMTS.2011.6137100  0.379
2011 Chauhan YS, Lu DD, Venugopalan S, Karim MA, Niknejad A, Hu C. Compact models for sub-22nm MOSFETs Technical Proceedings of the 2011 Nsti Nanotechnology Conference and Expo, Nsti-Nanotech 2011. 2: 720-725.  0.373
2010 Yao S, Morshed TH, Lu DD, Venugopalan S, Xiong W, Cleavelin CR, Niknejad AM, Hu C. Global parameter extraction for a multi-gate MOSFETs compact model Ieee International Conference On Microelectronic Test Structures. 194-197. DOI: 10.1109/ICMTS.2010.5466821  0.326
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