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Nur A. Touba - Publications

Affiliations: 
Electrical and Computer Engineering (Computer Engineering) University of Texas at Austin, Austin, Texas, U.S.A. 
Area:
Electronics and Electrical Engineering
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84 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Das A, Touba NA. A Single Error Correcting Code with One-Step Group Partitioned Decoding Based on Shared Majority-Vote Electronics. 9: 709. DOI: 10.3390/Electronics9050709  0.312
2020 Das A, Touba NA. A New Class of Single Burst Error Correcting Codes with Parallel Decoding Ieee Transactions On Computers. 69: 253-259. DOI: 10.1109/Tc.2019.2947425  0.307
2019 Das A, Sanchez-Macian A, Garcia-Herrero F, Touba NA, Maestro JA. Enhanced Limited Magnitude Error Correcting Codes for Multilevel Cell Main Memories Ieee Transactions On Nanotechnology. 18: 1023-1026. DOI: 10.1109/Tnano.2019.2945341  0.324
2019 Das A, Touba NA. Efficient One-Step Decodable Limited Magnitude Error Correcting Codes for Multilevel Cell Main Memories Ieee Transactions On Nanotechnology. 18: 575-583. DOI: 10.1109/Tnano.2019.2917139  0.316
2017 Lee T, Touba NA, Yang J. Enhancing Test Compression With Dependency Analysis for Multiple Expansion Ratios Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 36: 1571-1579. DOI: 10.1109/Tcad.2017.2681063  0.504
2016 Yang JS, Chung J, Touba NA. Enhancing Superset X-Canceling Method with Relaxed Constraints on Fault Observation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 298-308. DOI: 10.1109/Tcad.2015.2459035  0.307
2015 Muthyala SS, Touba NA. Reducing test time for 3D-ICs by improved utilization of test elevators Ieee/Ifip International Conference On Vlsi and System-On-Chip, Vlsi-Soc. 2015. DOI: 10.1109/VLSI-SoC.2014.7004157  0.402
2015 Muthyala SS, Touba NA. Improving test compression with scan feedforward techniques Proceedings - International Test Conference. 2015. DOI: 10.1109/TEST.2014.7035358  0.416
2015 Muthyala SS, Touba NA. Efficient utilization of test elevators to reduce test time in 3D-ICs Ifip Advances in Information and Communication Technology. 464: 21-38. DOI: 10.1007/978-3-319-25279-7_2  0.366
2014 Yang JS, Touba NA. Test point insertion with control point by greater use of existing functional flip-flops Etri Journal. 36: 942-952. DOI: 10.4218/Etrij.14.0113.1121  0.683
2014 Yang JS, Lee J, Touba NA. Utilizing ATE vector repeat with linear decompressor for test vector compression Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 33: 1219-1230. DOI: 10.1109/Tcad.2014.2314307  0.678
2014 Saleem K, Touba NA. Efficient algorithm for test vector decompression using an embedded processor Autotestcon (Proceedings). 360-364. DOI: 10.1109/AUTEST.2014.6935172  0.41
2013 Muthyala SS, Touba NA. SOC test compression scheme using sequential linear decompressors with retained free variables Proceedings of the Ieee Vlsi Test Symposium. DOI: 10.1109/VTS.2013.6548884  0.435
2013 Yang JS, Touba NA. Improved trace buffer observation via selective data capture using 2-D compaction for post-silicon debug Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 21: 320-328. DOI: 10.1109/Tvlsi.2012.2183399  0.364
2013 Lee YW, Touba NA. Unified 3D test architecture for variable test data bandwidth across pre-bond, partial stack, and post-bond test Proceedings - Ieee International Symposium On Defect and Fault Tolerance in Vlsi Systems. 184-189. DOI: 10.1109/DFT.2013.6653604  0.398
2013 Bawa AA, Rab MT, Touba NA. Efficient compression of x-masking control data via dynamic channel allocation Proceedings - Ieee International Symposium On Defect and Fault Tolerance in Vlsi Systems. 125-130. DOI: 10.1109/DFT.2013.6653594  0.301
2012 Muthyala SS, Touba NA. Improving test compression by retaining non-pivot free variables in sequential linear decompressors Proceedings - International Test Conference. DOI: 10.1109/TEST.2012.6401557  0.36
2012 Yang JS, Touba NA. X-Canceling MISR architectures for output response compaction with unknown values Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 1417-1427. DOI: 10.1109/Tcad.2012.2193579  0.328
2012 Yang JS, Touba NA. Efficient trace signal selection for silicon debug by error transmission analysis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 442-446. DOI: 10.1109/Tcad.2011.2171184  0.355
2012 Yang JS, Touba NA, Nadeau-Dostie B. Test point insertion with control points driven by existing functional flip-flops Ieee Transactions On Computers. 61: 1473-1483. DOI: 10.1109/Tc.2011.189  0.437
2010 Lee J, Touba NA. Correlation-based rectangular encoding Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 1483-1492. DOI: 10.1109/Tvlsi.2009.2025882  0.673
2010 Wu S, Wang LT, Yu L, Furukawa H, Wen X, Jone WB, Touba NA, Zhao F, Liu J, Chao HJ, Li F, Jiang Z. Logic BIST architecture using staggered launch-on-shift for testing designs containing asynchronous clock domains Proceedings - Ieee International Symposium On Defect and Fault Tolerance in Vlsi Systems. 358-366. DOI: 10.1109/DFT.2010.50  0.315
2009 Yang JS, Benoit ND, Touba NA. Test point insertion using functional flip-flops to drive control points Proceedings - International Test Conference. DOI: 10.1109/TEST.2009.5355688  0.35
2009 Yang JS, Nadeau-Dostie B, Touba NA. Reducing test point area for BIST through greater use of functional flip-flops to drive control points Proceedings - Ieee International Symposium On Defect and Fault Tolerance in Vlsi Systems. 20-28. DOI: 10.1109/DFT.2009.33  0.344
2008 Young D, Touba NA. Proceedings - International Test Conference: Welcome Message Proceedings - International Test Conference. DOI: 10.1109/TEST.2008.4700532  0.337
2008 Davidson S, Touba NA. Guest editors' introduction: Progress in test compression Ieee Design and Test of Computers. 25: 112-113. DOI: 10.1109/Mdt.2008.38  0.515
2008 Touba NA. ITC 2008 Highlights Ieee Design & Test of Computers. 25: 398-399. DOI: 10.1109/Mdt.2008.144  0.353
2008 Girard P, Wen X, Touba NA. Low-Power Testing System-On-Chip Test Architectures. 307-350. DOI: 10.1016/B978-012373973-5.50012-7  0.427
2008 Wang LT, Stroud CE, Touba NA. System-on-Chip Test Architectures System-On-Chip Test Architectures.  0.41
2007 Dutta A, Touba NA. Using limited dependence sequential expansion for decompressing test vectors Proceedings - International Test Conference. DOI: 10.1109/TEST.2006.297662  0.315
2007 Balakrishnan KJ, Touba NA. Relationship between entropy and test data compression Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 386-395. DOI: 10.1109/Tcad.2006.882600  0.784
2007 Lee J, Touba NA. LFSR-reseeding scheme achieving low-power dissipation during test Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 396-401. DOI: 10.1109/Tcad.2006.882509  0.699
2007 Lee J, Touba NA. Reducing shift cycles and test power using linear feedforward network Autotestcon (Proceedings). 253-259. DOI: 10.1109/AUTEST.2006.283646  0.44
2006 Lee J, Touba NA. Combining linear and non-linear test vector compression using correlation-based rectangular encoding Proceedings of the Ieee Vlsi Test Symposium. 2006: 252-257. DOI: 10.1109/VTS.2006.25  0.368
2006 Balakrishnan KJ, Touba NA. Improving linear test data compression Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 14: 1227-1237. DOI: 10.1109/Tvlsi.2006.886417  0.791
2006 MacDonald E, Touba NA. Delay testing of partially depleted silicon-on-insulator (PD-SOI) circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 14: 587-594. DOI: 10.1109/Tvlsi.2006.878209  0.667
2006 Touba NA. Survey of test vector compression techniques Ieee Design and Test of Computers. 23: 294-303. DOI: 10.1109/Mdt.2006.105  0.453
2006 Dutta A, Touba NA. Synthesis of efficient linear test pattern generators Proceedings - Ieee International Symposium On Defect and Fault Tolerance in Vlsi Systems. 206-214. DOI: 10.1109/DFT.2006.61  0.349
2006 Lee J, Touba NA. Efficiently utilizing ATE vector repeat for compression by scan vector decomposition Proceedings of the Asian Test Symposium. 2006: 237-242. DOI: 10.1109/ATS.2006.261026  0.305
2006 Li X, Lee KJ, Touba NA. Test compression Vlsi Test Principles and Architectures. 341-396. DOI: 10.1016/B978-012370597-6/50010-X  0.438
2005 Ghosh S, Basu S, Touba NA. Selecting Error Correcting Codes to Minimize Power in Memory Checker Circuits Journal of Low Power Electronics. 1: 63-72. DOI: 10.1166/Jolpe.2005.007  0.746
2005 Touba NA. Methods for improving test compression Proceedings - International Test Conference. 2005: 1292-1293. DOI: 10.1109/TEST.2005.1584115  0.307
2005 Dutta A, Rodrigues T, Touba NA. Low cost test vector compression/decompression scheme for circuits with a reconfigurable serial multiplier Proceedings - Ieee Computer Society Annual Symposium On Vlsi - New Frontiers in Vlsi. 200-205. DOI: 10.1109/ISVLSI.2005.49  0.425
2005 Balakrishnan KJ, Touba NA. Reconfigurable linear decompressors using symbolic gaussian elimination Proceedings -Design, Automation and Test in Europe, Date '05. 1130-1135. DOI: 10.1109/DATE.2005.255  0.749
2005 Kalyanam VK, Touba NA. HTPG: Hybrid test pattern generation for reducing test storage Autotestcon (Proceedings). 2005: 759-765. DOI: 10.1109/AUTEST.2005.1609232  0.42
2005 Balakrishnan KJ, Touba NA, Patil S. Compressing functional tests for microprocessors Proceedings of the Asian Test Symposium. 2005: 428-433. DOI: 10.1109/ATS.2005.38  0.782
2005 Lee J, Touba NA. Low power BIST based on scan partitioning Proceedings - Ieee International Symposium On Defect and Fault Tolerance in Vlsi Systems. 33-41.  0.32
2004 Krishna CV, Jas A, Touba NA. Achieving high encoding efficiency with partial dynamic LFSR reseeding Acm Transactions On Design Automation of Electronic Systems. 9: 500-516. DOI: 10.1145/1027084.1027089  0.739
2004 Krishna CV, Touba NA. 3-stage variable length continuous-flow scan vector decompression scheme Proceedings of the Ieee Vlsi Test Symposium. 79-86. DOI: 10.1109/VTEST.2004.1299229  0.315
2004 Jas A, Krishna CV, Touba NA. Weighted pseudorandom hybrid BIST Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 12: 1277-1283. DOI: 10.1109/Tvlsi.2004.837985  0.791
2004 Mohanram K, Touba NA. Lowering power consumption in concurrent checkers via input ordering Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 12: 1234-1243. DOI: 10.1109/Tvlsi.2004.836318  0.656
2004 Jas A, Pouya B, Touba NA. Test data compression technique for embedded cores using virtual scan chains Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 12: 775-780. DOI: 10.1109/Tvlsi.2004.830911  0.767
2004 Balakrishnan KJ, Touba NA. Relating entropy theory to test data compression Proceedings - Ninth Ieee European Test Symposium, Ets 2004. 94-99. DOI: 10.1109/ETSYM.2004.1347615  0.78
2004 Balakrishnan K, Touba NA. Matrix-based software test data decompression for systems-on-a-chip Journal of Systems Architecture. 50: 247-256. DOI: 10.1016/J.Sysarc.2003.08.007  0.815
2004 Lee J, Touba NA. Low power test data compression based on LFSR reseeding Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 180-185.  0.415
2004 Balakrishnan KJ, Touba NA. Improving encoding efficiency for linear decompressors using scan inversion Proceedings - International Test Conference. 936-944.  0.77
2003 Li L, Chakrabarty K, Touba NA. Test Data Compression Using Dictionaries with Selective Entries and Fixed-Length Indices Acm Transactions On Design Automation of Electronic Systems. 8: 470-490. DOI: 10.1145/944027.944032  0.547
2003 Balakrishnan KJ, Touba NA. Deterministic test vector decompression in software using linear operations [SOC testing] Proceedings of the Ieee Vlsi Test Symposium. 2003: 225-231. DOI: 10.1109/VTEST.2003.1197655  0.819
2003 Mohanram K, Touba NA. Eliminating non-determinism during test of high-speed source synchronous differential buses Proceedings of the Ieee Vlsi Test Symposium. 2003: 121-127. DOI: 10.1109/VTEST.2003.1197642  0.648
2003 Mohanram K, Touba NA. Partial error masking to reduce soft error failure rate in logic circuits Proceedings - Ieee International Symposium On Defect and Fault Tolerance in Vlsi Systems. 2003: 433-440. DOI: 10.1109/TSM.2005.1250141  0.581
2003 Balakrishnan KJ, Touba NA. Scan-based BIST diagnosis using an embedded processor Proceedings - Ieee International Symposium On Defect and Fault Tolerance in Vlsi Systems. 2003: 209-215. DOI: 10.1109/TSM.2005.1250114  0.347
2003 Jas A, Ghosh-Dastidar J, Ng ME, Touba NA. An efficient test vector compression scheme using selective huffman coding Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 22: 797-806. DOI: 10.1109/Tcad.2003.811452  0.795
2003 Mohanram K, Sogomonyan ES, Gössel M, Touba NA. Synthesis of low-cost parity-based partially self-checking circuits Proceedings - 9th Ieee International On-Line Testing Symposium, Iolts 2003. 35-40. DOI: 10.1109/OLT.2003.1214364  0.617
2003 Ghosh S, Basu S, Touba NA. Joint minimization of power and area in scan testing by scan cell reordering Proceedings of Ieee Computer Society Annual Symposium On Vlsi, Isvlsi. 2003: 246-249. DOI: 10.1109/ISVLSI.2003.1183485  0.339
2003 Mohanram K, Touba NA. Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits Ieee International Test Conference (Tc). 893-901.  0.597
2003 Krishna CV, Touba NA. Adjustable Width Linear Combinational Scan Vector Decompression Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 863-866.  0.307
2002 Sankaralingam R, Touba NA. Controlling peak power during scan testing Proceedings of the Ieee Vlsi Test Symposium. 2002: 153-159. DOI: 10.1109/VTS.2002.1011127  0.753
2002 MacDonald E, Touba NA. Very low voltage testing of SOI integrated circuits Proceedings of the Ieee Vlsi Test Symposium. 2002: 25-30. DOI: 10.1109/VTS.2002.1011106  0.332
2002 Touba NA. Circular BIST with state skipping Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 10: 668-672. DOI: 10.1109/Tvlsi.2002.801564  0.402
2002 Balakrishnan KJ, Touba NA. Matrix-based test vector decompression using an embedded processor Proceedings - Ieee International Symposium On Defect and Fault Tolerance in Vlsi Systems. 2002: 159-165. DOI: 10.1109/DFTVS.2002.1173512  0.813
2002 Sankaralingam R, Touba NA. Inserting test points to control peak power during scan testing Proceedings - Ieee International Symposium On Defect and Fault Tolerance in Vlsi Systems. 2002: 138-146. DOI: 10.1109/DFTVS.2002.1173510  0.787
2002 Mohanram K, Touba NA. Input ordering in concurrent checkers to reduce power consumption Proceedings - Ieee International Symposium On Defect and Fault Tolerance in Vlsi Systems. 2002: 87-95. DOI: 10.1109/DFTVS.2002.1173505  0.621
2002 Sankaralingam R, Touba NA. Reducing test power during test using programmable scan chain disable Proceedings - 1st Ieee International Workshop On Electronic Design, Test and Applications, Delta 2002. 159-163. DOI: 10.1109/DELTA.2002.994606  0.789
2002 Jas A, Touba NA. Deterministic test vector compression/decompression for systems-on-a-chip using an embedded processor Journal of Electronic Testing: Theory and Applications (Jetta). 18: 503-514. DOI: 10.1023/A:1016505926570  0.797
2002 Krishna CV, Touba NA. Reducing test data volume using LFSR reseeding with seed compression Ieee International Test Conference (Tc). 321-330.  0.322
2002 Mohanram K, Krishna CV, Touba NA. A methodology for automated insertion of concurrent error detection hardware in synthesizable Verilog RTL Proceedings - Ieee International Symposium On Circuits and Systems. 1: I/577-I/580.  0.594
2001 Touba NA, McCluskey EJ. Bit-fixing in pseudorandom sequences for scan BIST Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 20: 545-555. DOI: 10.1109/43.918212  0.649
2001 Jas A, Krishna CV, Touba NA. Hybrid BIST based on weighted pseudo-random testing: A new test resource partitioning scheme Proceedings of the Ieee Vlsi Test Symposium. 2-8.  0.784
2001 Sankaralingam R, Pouya B, Touba NA. Reducing power dissipation during test using scan chain disable Proceedings of the Ieee Vlsi Test Symposium. 319-324.  0.785
2001 Krishna CV, Jas A, Touba NA. Test vector encoding using partial LFSR reseeding Ieee International Test Conference (Tc). 885-893.  0.754
1999 Touba NA, McCluskey EJ. RP-SYN: synthesis of random pattern testable circuits with test point insertion Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 18: 1202-1213. DOI: 10.1109/43.775638  0.644
1998 Pouya B, Touba NA. Synthesis of zero-aliasing elementary-tree space compactors Proceedings of the Ieee Vlsi Test Symposium. 70-77.  0.787
1997 Touba NA, Pouya B. Using partial isolation rings to test core-based designs Ieee Design and Test of Computers. 14: 52-59. DOI: 10.1109/54.632881  0.752
1997 Touba NA, McCluskey EJ. Logic synthesis of multilevel circuits with concurrent error detection Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 16: 783-789. DOI: 10.1109/43.644041  0.61
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