Jun J. Kong, Ph.D. - Publications
Affiliations: | 2005 | University of Minnesota, Twin Cities, Minneapolis, MN |
Area:
Electronics and Electrical EngineeringYear | Citation | Score | |||
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2004 | Kong JJ, Parhi KK. Low-latency architectures for high-throughput rate Viterbi decoders Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 12: 642-651. DOI: 10.1109/Tvlsi.2004.827600 | 0.507 | |||
2004 | Kong JJ, Parhi KK. Quantum convolutional codes design and their encoder architectures Conference Record - Asilomar Conference On Signals, Systems and Computers. 1: 1131-1135. | 0.413 | |||
2003 | Kong JJ, Parhi KK. Interleaved convolutional code and its Viterbi decoder architecture Eurasip Journal On Applied Signal Processing. 2003: 1328-1334. DOI: 10.1155/S1110865703309126 | 0.491 | |||
2003 | Kong JJ, Parhi KK. K-nested layered look-ahead method and architectures for high throughput Viterbi decoder Ieee Workshop On Signal Processing Systems, Sips: Design and Implementation. 2003: 99-104. DOI: 10.1109/SIPS.2003.1235651 | 0.463 | |||
2003 | Kong JJ, Parhi KK. Interleaved cyclic redundancy check (CRC) code Conference Record of the Asilomar Conference On Signals, Systems and Computers. 2: 2137-2141. | 0.449 | |||
2002 | Kong JJ, Parhi KK. Viterbi decoder architecture for interleaved convolutional code Conference Record of the Asilomar Conference On Signals, Systems and Computers. 2: 1934-1937. | 0.464 | |||
2001 | Choi SH, Kong JJ. State parallel Viterbi decoder soft IP and its applications Ieee Region 10 International Conference On Electrical and Electronic Technology. 355-358. | 0.309 | |||
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