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Rajit Manohar - Publications

Affiliations: 
Cornell University, Ithaca, NY, United States 
Area:
Electronics and Electrical Engineering, Computer Science
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40 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Manohar R. Exact Timing Analysis for Asynchronous Circuits with Multiple Periods Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 1-1. DOI: 10.1109/Tcad.2019.2963271  0.382
2019 Bingham N, Manohar R. Self-Timed Adaptive Digit-Serial Addition Ieee Transactions On Very Large Scale Integration Systems. 27: 2131-2141. DOI: 10.1109/Tvlsi.2019.2918441  0.463
2019 Srivastava N, Manohar R. Operation-Dependent Frequency Scaling Using Desynchronization Ieee Transactions On Very Large Scale Integration Systems. 27: 799-809. DOI: 10.1109/Tvlsi.2018.2885335  0.46
2019 Bingham N, Manohar R. QDI Constant-Time Counters Ieee Transactions On Very Large Scale Integration Systems. 27: 83-91. DOI: 10.1109/Tvlsi.2018.2867289  0.467
2019 Moradi S, Manohar R. The impact of on-chip communication on memory technologies for neuromorphic systems Journal of Physics D. 52: 14003. DOI: 10.1088/1361-6463/Aae641  0.48
2018 Hua W, Manohar R. Exact Timing Analysis for Asynchronous Systems Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 203-216. DOI: 10.1109/Tcad.2017.2693268  0.42
2018 Chen Y, Zhang X, Lian Y, Manohar R, Tsividis Y. A Continuous-Time Digital IIR Filter With Signal-Derived Timing and Fully Agile Power Consumption Ieee Journal of Solid-State Circuits. 53: 418-430. DOI: 10.1109/Jssc.2017.2769339  0.332
2015 Longfield S, Nkounkou B, Manohar R, Tate R. Preventing glitches and short circuits in high-level self-timed chip specifications Acm Sigplan Notices. 50: 270-279. DOI: 10.1145/2813885.2737967  0.3
2015 Akopyan F, Sawada J, Cassidy A, Alvarez-Icaza R, Arthur J, Merolla P, Imam N, Nakamura Y, Datta P, Nam GJ, Taba B, Beakes M, Brezzo B, Kuang JB, Manohar R, et al. TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 34: 1537-1557. DOI: 10.1109/Tcad.2015.2474396  0.759
2015 Manohar R. Comparing Stochastic and Deterministic Computing Ieee Computer Architecture Letters. 14: 119-122. DOI: 10.1109/Lca.2015.2412553  0.38
2015 Rovere G, Bartolozzi C, Imam N, Manohar R. Design of a QDI asynchronous AER serializer/deserializer link in 180nm for event-based sensors for robotic applications Proceedings - Ieee International Symposium On Circuits and Systems. 2015: 2712-2715. DOI: 10.1109/ISCAS.2015.7169246  0.329
2015 Ortega Otero CT, Tse J, Manohar R. AES hardware-software co-design in WSN Proceedings - International Symposium On Asynchronous Circuits and Systems. 2015: 85-92. DOI: 10.1109/ASYNC.2015.21  0.353
2014 Merolla PA, Arthur JV, Alvarez-Icaza R, Cassidy AS, Sawada J, Akopyan F, Jackson BL, Imam N, Guo C, Nakamura Y, Brezzo B, Vo I, Esser SK, Appuswamy R, Taba B, ... ... Manohar R, et al. Artificial brains. A million spiking-neuron integrated circuit with a scalable communication network and interface. Science (New York, N.Y.). 345: 668-73. PMID 25104385 DOI: 10.1126/Science.1254642  0.74
2014 Guimbretiére F, Liu S, Wang H, Manohar R. An asymmetric dual-processor architecture for low-power information appliances Acm Transactions in Embedded Computing Systems. 13: 98. DOI: 10.1145/2560538  0.387
2013 Karmazin R, Otero CTO, Manohar R. cellTK: Automated layout for asynchronous circuits with nonstandard cells Proceedings - International Symposium On Asynchronous Circuits and Systems. 58-66. DOI: 10.1109/ASYNC.2013.27  0.402
2013 Longfield S, Manohar R. Inverting Martin synthesis for verification Proceedings - International Symposium On Asynchronous Circuits and Systems. 150-157. DOI: 10.1109/ASYNC.2013.10  0.313
2012 Imam N, Cleland TA, Manohar R, Merolla PA, Arthur JV, Akopyan F, Modha DS. Implementation of olfactory bulb glomerular-layer computations in a digital neurosynaptic core. Frontiers in Neuroscience. 6: 83. PMID 22685425 DOI: 10.3389/Fnins.2012.00083  0.711
2012 Harris TR, Priyadarshi S, Melamed S, Ortega C, Manohar R, Dooley SR, Kriplani NM, Davis WR, Franzon PD, Steer MB. A transient electrothermal analysis of three-dimensional integrated circuits Ieee Transactions On Components, Packaging and Manufacturing Technology. 2: 660-667. DOI: 10.1109/Tcpmt.2011.2178414  0.385
2012 Sheikh BR, Manohar R. An asynchronous floating-point multiplier Proceedings - International Symposium On Asynchronous Circuits and Systems. 89-96. DOI: 10.1109/ASYNC.2012.19  0.365
2012 Priyadarshi S, Harris TR, Melamed S, Otero C, Kriplani NM, Christoffersen CE, Manohar R, Dooley SR, Davis WR, Franzon PD, Steer MB. Dynamic electrothermal simulation of three-dimensional integrated circuits using standard cell macromodels Iet Circuits, Devices and Systems. 6: 35-44. DOI: 10.1049/Iet-Cds.2011.0061  0.401
2011 Sheikh BR, Manohar R. Energy-Efficient pipeline templates for high-performance asynchronous circuits Acm Journal On Emerging Technologies in Computing Systems. 7. DOI: 10.1145/2043643.2043649  0.447
2011 Imam N, Manohar R. Address-event communication using token-ring mutual exclusion Proceedings - International Symposium On Asynchronous Circuits and Systems. 99-108. DOI: 10.1109/ASYNC.2011.20  0.382
2010 Sheikh BR, Manohar R. An operand-optimized asynchronous IEEE 754 double-precision floating-point adder Proceedings - International Symposium On Asynchronous Circuits and Systems. 151-162. DOI: 10.1109/ASYNC.2010.24  0.309
2009 LaFrieda C, Manohar R. Reducing power consumption with relaxed quasi delay-insensitive circuits Proceedings - International Symposium On Asynchronous Circuits and Systems. 217-226. DOI: 10.1109/ASYNC.2009.9  0.319
2009 Ramaswamy S, Rockett L, Patel D, Danziger S, Manohar R, Kelly CW, Holt JL, Ekanayake V, Elftmann D. A radiation hardened reconfigurable FPGA Ieee Aerospace Conference Proceedings. DOI: 10.1109/AERO.2009.4839506  0.609
2006 Fang D, Akopyan F, Manohar R. Self-timed thermally-aware circuits Proceedings - Ieee Computer Society Annual Symposium On Emerging Vlsi Technologies and Architectures 2006. 2006: 438-439. DOI: 10.1109/ISVLSI.2006.81  0.327
2006 Manohar R. Reconfigurable asynchronous logic Proceedings of the Custom Integrated Circuits Conference. 13-20. DOI: 10.1109/CICC.2006.320939  0.393
2006 Peng S, Manohar R. Yield enhancement of asynchronous logic circuits through 3-Dimensional integration technology Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 2006: 159-164.  0.33
2005 Fang D, Teifel J, Manohar R. A high-performance asynchronous FPGA: Test results Proceedings - 13th Annual Ieee Symposium On Field-Programmable Custom Computing Machines, Fccm 2005. 2005: 271-272. DOI: 10.1109/FCCM.2005.9  0.328
2005 Ekanayake VN, Kelly C, Manohar R. BitSNAP: Dynamic significance compression for a low-energy sensor network asynchronous processor Proceedings - International Symposium On Asynchronous Circuits and Systems. 144-154. DOI: 10.1109/ASYNC.2005.14  0.747
2004 Ekanayake V, Kelly C, Manohar R. An ultra low-power processor for sensor networks Operating Systems Review (Acm). 38: 27-36. DOI: 10.1145/1037949.1024397  0.329
2004 Teifel J, Manohar R. An asynchronous dataflow FPGA architecture Ieee Transactions On Computers. 53: 1376-1392. DOI: 10.1109/Tc.2004.88  0.624
2004 Fang D, Manohar R. Non-uniform access asynchronous register files Proceedings of the International Symposium On Advanced Research in Asynchronous Circuits and Systems. 10: 75-85.  0.334
2004 Teifel J, Manohar R. Highly pipelined asynchronous FPGAs Acm/Sigda International Symposium On Field Programmable Gate Arrays - Fpga. 12: 133-142.  0.359
2003 Ekanayake VN, Manohar R. Asynchronous DRAM design and synthesis Proceedings - International Symposium On Asynchronous Circuits and Systems. 174-183. DOI: 10.1109/ASYNC.2003.1199177  0.774
2003 Teifel J, Manohar R. A high-speed clockless serial link transceiver Proceedings - International Symposium On Asynchronous Circuits and Systems. 151-161. DOI: 10.1109/ASYNC.2003.1199175  0.375
2003 Teifel J, Manohar R. Programmable asynchronous pipeline arrays Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 2778: 345-354.  0.418
2001 Manohar R. Width-adaptive data word architectures Proceedings - 2001 Conference On Advanced Research in Vlsi, Arvlsi 2001. 112-129. DOI: 10.1109/ARVLSI.2001.915555  0.347
2001 Manohar R, Nyström M, Martin AJ. Precise exceptions in asynchronous processors Proceedings - 2001 Conference On Advanced Research in Vlsi, Arvlsi 2001. 16-28. DOI: 10.1109/ARVLSI.2001.915547  0.348
2001 Manohar R, Kelly C. Network on a chip: Modeling wireless networks with asynchronous VLSI Ieee Communications Magazine. 39: 149-155. DOI: 10.1109/35.965373  0.694
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