| Year |
Citation |
Score |
| 2013 |
Callegari S, Pareschi F, Setti G, Soma M. On the usage of resonate and fire dynamics in the complex oscillation-based test approach International Journal of Circuit Theory and Applications. 41: 1290-1317. DOI: 10.1002/Cta.1857 |
0.338 |
|
| 2010 |
Callegari S, Pareschi F, Setti G, Soma M. Complex oscillation-based test and its application to analog filters Ieee Transactions On Circuits and Systems I: Regular Papers. 57: 956-969. DOI: 10.1109/Tcsi.2010.2046956 |
0.438 |
|
| 2010 |
Soma M, Wang Q, Ichiyama K, Ishida M, Yamaguchi TJ. Case studies in on-chip BIST for high-frequency circuits and systems Midwest Symposium On Circuits and Systems. 465-468. DOI: 10.1109/MWSCAS.2010.5548730 |
0.392 |
|
| 2006 |
Wang Q, Tang Y, Soma M. Method to measure RF transceiver bandwidth in the time domain Ieee Transactions On Instrumentation and Measurement. 55: 982-988. DOI: 10.1109/Tim.2006.873789 |
0.424 |
|
| 2005 |
Taylor KA, Nelson B, Chong A, Lin H, Chan E, Soma M, Haggag H, Huard J, Braatz J. Special issue on BIT CMOS built-in test architecture for high-speed jitter measurement Ieee Transactions On Instrumentation and Measurement. 54: 975-987. DOI: 10.1109/Tim.2005.847348 |
0.434 |
|
| 2004 |
Yamaguchi TJ, Soma M, Nissen JP, Halter DE, Raina R, Ishida M. Skew measurements in clock distribution circuits using an analytic signal method Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 997-1009. DOI: 10.1109/Tcad.2004.829814 |
0.348 |
|
| 2003 |
Yamaguchi TJ, Soma M, Ishida M, Watanabe T, Ohmi T. Extraction of instantaneous and RMS sinusoidal jitter using an analytic signal method Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 50: 288-298. DOI: 10.1109/Tcsii.2003.812916 |
0.34 |
|
| 2003 |
Yamaguchi TJ, Ishida M, Soma M, Malarsie L, Musha H. Timing Jitter Measurement of Intrinsic Random Jitter and Sinusoidal Jitter Using Frequency Division Journal of Electronic Testing. 19: 183-193. DOI: 10.1023/A:1022897825759 |
0.379 |
|
| 2001 |
Kim S, Soma M. An all-digital built-in self-test for high-speed phase-locked loops Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 48: 141-150. DOI: 10.1109/82.917782 |
0.555 |
|
| 1999 |
Devarayanadurg G, Soma M, Goteti P, Huynh SD. Test set selection for structural faults in analog IC's Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 18: 1026-1039. DOI: 10.1109/43.771183 |
0.37 |
|
| 1998 |
Soma M. Mixed-signal on-chip timing measurements Integration. 26: 151-165. DOI: 10.1016/S0167-9260(98)00026-1 |
0.415 |
|
| 1997 |
Park HJ, Soma M. Analytical model for switching transitions of submicron CMOS logics Ieee Journal of Solid-State Circuits. 32: 880-889. DOI: 10.1109/4.585290 |
0.44 |
|
| 1996 |
Charoenrook A, Soma M. A fault diagnosis technique for flash ADC's Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 43: 445-457. DOI: 10.1109/82.502317 |
0.313 |
|
| 1994 |
Devarayanadurg GV, Soma M. An interconnect model for arbitrary terminations based on scattering parameters Analog Integrated Circuits and Signal Processing. 5: 31-45. DOI: 10.1007/Bf01673904 |
0.39 |
|
| 1992 |
Henling B, Soma M. C-configurability and built-in-test of reconfigurable processor array interconnection networks Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 39: 302-311. DOI: 10.1109/82.142031 |
0.377 |
|
| 1990 |
Katoozi M, Soma M. Built-in test of CMOS state machines with realistic faults: a system perspective Ieee Journal of Solid-State Circuits. 25: 482-489. DOI: 10.1109/4.52173 |
0.446 |
|
| 1988 |
Katoozi M, Soma M. A testable CMOS synchronous counter Ieee Journal of Solid-State Circuits. 23: 1241-1248. DOI: 10.1109/4.5951 |
0.395 |
|
| 1987 |
Soma M, Galbraith DC, White RL. Radio-frequency coils in implantable devices: misalignment analysis and design procedure. Ieee Transactions On Bio-Medical Engineering. 34: 276-82. PMID 3504201 DOI: 10.1109/Tbme.1987.326088 |
0.368 |
|
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