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Sung-Mo Kang, Ph.D. - Publications

Affiliations: 
Rutgers University, New Brunswick, New Brunswick, NJ, United States 
 1985-2000 Department of electrical and computer engineering University of Illinois, Urbana-Champaign, Urbana-Champaign, IL 
 2001-2007 Baskin School of Engineering University of California, Santa Cruz, Santa Cruz, CA, United States 
 2013-2017 Korea Advanced Institute of Science and Technology, Daejeon, South Korea 
Area:
Modeling and simulation of semiconductor devices and circuits
Website:
https://nisl.soe.ucsc.edu/
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54 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Ascoli A, Tetzlaff R, Kang S, Chua LO. Theoretical Foundations of Memristor Cellular Nonlinear Networks: A DRM 2 -Based Method to Design Memcomputers With Dynamic Memristors Ieee Transactions On Circuits and Systems. 67: 2753-2766. DOI: 10.1109/Tcsi.2020.2978460  0.482
2017 Eshraghian JK, Cho K, Iu HHC, Fernando T, Iannella N, Kang S, Eshraghian K. Maximization of Crossbar Array Memory Using Fundamental Memristor Theory Ieee Transactions On Circuits and Systems Ii-Express Briefs. 64: 1402-1406. DOI: 10.1109/Tcsii.2017.2767078  0.323
2014 Ziabari A, Park JH, Ardestani EK, Renau J, Kang SM, Shakouri A. Power blurring: Fast static and transient thermal analysis method for packaged integrated circuits and power devices Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 22: 2366-2379. DOI: 10.1109/Tvlsi.2013.2293422  0.4
2014 Lee SJ, Kim SJ, Cho K, Kang SM, Eshraghian K. Complementary resistive switch-based smart sensor search engine Ieee Sensors Journal. 14: 1639-1646. DOI: 10.1109/Jsen.2013.2296972  0.325
2013 Shin S, Kim K, Kang S. Resistive Computing: Memristors-Enabled Signal Multiplication Ieee Transactions On Circuits and Systems I-Regular Papers. 60: 1241-1249. DOI: 10.1109/Tcsi.2013.2244434  0.368
2013 Shin S, Zheng L, Weickhardt G, Cho S, Kang S. Compact Circuit Model and Hardware Emulation for Floating Memristor Devices Ieee Circuits and Systems Magazine. 13: 42-55. DOI: 10.1109/Mcas.2013.2256259  0.414
2012 Shin SH, Kim K, Kang S. Memristive XOR for resistive multiplier Electronics Letters. 48: 78-80. DOI: 10.1049/El.2011.3270  0.355
2012 Jung J, Shin S, Lim S, Kim S, Kang S. Power efficient high-speed DAC for wideband communication applications Analog Integrated Circuits and Signal Processing. 70: 421-428. DOI: 10.1007/S10470-011-9708-4  0.426
2011 Bong J, Jo K, Min K, Kang S. Oxide-Tunneling Leakage Suppressed SRAM for Sub-65-nm Very Large Scale Integrated Circuits Journal of Low Power Electronics. 7: 87-95. DOI: 10.1166/Jolpe.2011.1119  0.34
2011 Shin S, Kim K, Kang S. Memristor Applications for Programmable Analog ICs Ieee Transactions On Nanotechnology. 10: 266-274. DOI: 10.1109/Tnano.2009.2038610  0.336
2011 Shin S, Kim K, Kang S. Reconfigurable Stateful nor Gate for Large-Scale Logic-Array Integrations Ieee Transactions On Circuits and Systems Ii-Express Briefs. 58: 442-446. DOI: 10.1109/Tcsii.2011.2158253  0.383
2011 Kim K, Shin S, Kang S. Field Programmable Stateful Logic Array Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 30: 1800-1813. DOI: 10.1109/Tcad.2011.2165067  0.379
2010 Jo KH, Jung CM, Min KS, Kang SM. Self-adaptive write circuit for low-power and variation-tolerant memristors Ieee Transactions On Nanotechnology. 9: 675-678. DOI: 10.1109/Tnano.2010.2052108  0.423
2010 Shin S, Kim K, Kang S. Data-Dependent Statistical Memory Model for Passive Array of Memristive Devices Ieee Transactions On Circuits and Systems Ii-Express Briefs. 57: 986-990. DOI: 10.1109/Tcsii.2010.2083191  0.388
2010 Shin S, Kim K, Kang S. Compact Models for Memristors Based on Charge-Flux Constitutive Relationships Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 590-598. DOI: 10.1109/Tcad.2010.2042891  0.347
2007 Shin S, Kim K, Lee K, Kang S. Fast- Frequency Offset Cancellation Loop Using Low-IF Receiver and Fractional-N PLL Ieee Transactions On Circuits and Systems Ii-Express Briefs. 54: 272-276. DOI: 10.1109/Tcsii.2006.888733  0.317
2005 Yang G, Jung S, Baek K, Kim SH, Kim S, Kang S. A 32-bit carry lookahead adder using dual-path all-N logic Ieee Transactions On Very Large Scale Integration Systems. 13: 992-996. DOI: 10.1109/Tvlsi.2005.853605  0.411
2004 Lee J, Huh Y, Bendix P, Kang S. Design of ESD power protection with diode structures for mixed-power supply systems Ieee Journal of Solid-State Circuits. 39: 260-264. DOI: 10.1109/Jssc.2003.820883  0.392
2004 Hwang I, Kim C, Kang S. A CMOS self-regulating VCO with low supply sensitivity Ieee Journal of Solid-State Circuits. 39: 42-48. DOI: 10.1109/Jssc.2003.820881  0.362
2004 Chen J, Kang S, Zou J, Liu C, Schutt-Aine JE. Reduced-order modeling of weakly nonlinear MEMS devices with Taylor-series expansion and Arnoldi approach Ieee\/Asme Journal of Microelectromechanical Systems. 13: 441-451. DOI: 10.1109/Jmems.2004.828704  0.359
2003 Kim K, Jung S, Kim T, Kang S. Minimum delay optimization for domino logic circuits---a coupling-aware approach Acm Transactions On Design Automation of Electronic Systems (Todaes). 8: 203-213. DOI: 10.1145/762488.762491  0.354
2003 Kim K, Jung S, Narayanan U, Liu CL, Kang S. Noise-aware interconnect power optimization in domino logic synthesis Ieee Transactions On Very Large Scale Integration Systems. 11: 79-89. DOI: 10.1109/Tvlsi.2002.801630  0.384
2003 Kim C, Kim K, Kang S. Energy-efficient skewed static logic with dual Vt: design and synthesis Ieee Transactions On Very Large Scale Integration Systems. 11: 64-70. DOI: 10.1109/Tvlsi.2002.800528  0.317
2003 Jung S, Kim K, Kang S. Timing constraints for domino logic gates with timing-dependent keepers Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 22: 96-103. DOI: 10.1109/Tcad.2002.805724  0.405
2003 Lee J, Kim K, Huh Y, Bendix P, Kang S. Chip-level charged-device modeling and simulation in CMOS integrated circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 22: 67-81. DOI: 10.1109/Tcad.2002.805720  0.437
2002 Kim K, Kim T, Hwang T, Kang S, Liu CL. Logic transformation for low-power synthesis Acm Transactions On Design Automation of Electronic Systems. 7: 265-283. DOI: 10.1145/544536.544539  0.388
2002 Jung S, Kim K, Kang S. Noise constrained transistor sizing and power optimization for dual V/sub t/ domino logic Ieee Transactions On Very Large Scale Integration Systems. 10: 532-541. DOI: 10.1109/Tvlsi.2002.801625  0.405
2002 Kim C, Jung S, Baek K, Kang S. High-speed CMOS circuits with parallel dynamic logic and speed-enhanced skewed static logic Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 49: 434-439. DOI: 10.1109/Tcsii.2002.802960  0.419
2002 Kim K, Kim T, Liu CL, Kang S. Domino logic synthesis based on implication graph Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 21: 232-240. DOI: 10.1109/43.980261  0.36
2002 Kim C, Kang S. A low-swing clock double-edge triggered flip-flop Ieee Journal of Solid-State Circuits. 37: 648-652. DOI: 10.1109/4.997859  0.359
2002 Jung S, Kang S. High performance dynamic logic incorporating gate voltage controlled keeper structure for wide fan-in gates Electronics Letters. 38: 852-853. DOI: 10.1049/El:20020623  0.383
2001 Kim K, Kang S. Crosstalk noise minimization in domino logic design Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 20: 1091-1100. DOI: 10.1109/43.945305  0.312
2001 Kim K, Jung S, Kim T, Kang S. Coupling-aware minimum delay optimisation for domino logic circuits Electronics Letters. 37: 813-814. DOI: 10.1049/El:20010554  0.363
2001 Hwang I, Kang S. Differential pass-transistor clocked flipflop Electronics Letters. 37: 732-734. DOI: 10.1049/El:20010530  0.4
2000 Cheng Y, Kang S. A temperature-aware simulation environment for reliable ULSI chip design Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 19: 1211-1220. DOI: 10.1109/43.875333  0.343
2000 Tsai C, Kang S. Cell-level placement for improving substrate thermal distribution Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 19: 253-266. DOI: 10.1109/43.828554  0.367
2000 Chen D, Li E, Rosenbaum E, Kang S. Interconnect thermal modeling for accurate simulation of circuit timing and reliability Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 19: 197-205. DOI: 10.1109/43.828548  0.359
2000 Baek K, Kim K, Kang S. EXODUS: inter-module bus-encoding scheme for system-on-a-chip Electronics Letters. 36: 615-617. DOI: 10.1049/El:20000482  0.346
1999 Yoo S, Kang S. Improved domino structures effective for high performance design Electronics Letters. 35: 367-368. DOI: 10.1049/El:19990276  0.338
1998 Yuan L, Teng C, Kang S. Statistical estimation of average power dissipation using nonparametric techniques Ieee Transactions On Very Large Scale Integration Systems. 6: 65-73. DOI: 10.1109/92.661249  0.341
1998 Cheng Y, Raha P, Teng C, Rosenbaum E, Kang S. ILLIADS-T: an electrothermal timing simulator for temperature-sensitive reliability diagnosis of CMOS VLSI chips Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 17: 668-681. DOI: 10.1109/43.712099  0.424
1997 Teng C, Cheng Y, Rosenbaum E, Kang S. iTEM: a temperature-dependent electromigration reliability diagnosis tool Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 16: 882-893. DOI: 10.1109/43.644613  0.323
1996 Xiang A, Wohlmuth W, Fay P, Kang SM, Adesida I. Modeling of InGaAs MSM photodetector for circuit-level simulation Journal of Lightwave Technology. 14: 716-723. DOI: 10.1109/50.495150  0.394
1996 Hill AM, Kang SM. Determining accuracy bounds for simulation-based switching activity estimation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 15: 611-618. DOI: 10.1109/43.503931  0.34
1995 Lockwood JW, Duan H, Morikuni JJ, Kang S, Akkineni S, Campbell RH. Scalable optoelectronic ATM networks: the iPOINT fully functional testbed Journal of Lightwave Technology. 13: 1093-1103. DOI: 10.1109/50.390225  0.316
1995 Leblebici Y, Unlu MS, Kang S, Onat BM. Transient simulation of heterojunction photodiodes-part I: computational methods Journal of Lightwave Technology. 13: 396-405. DOI: 10.1109/50.376717  0.578
1995 Brauer EJ, Kang S. An algorithm for functional verification of digital ECL circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 14: 1546-1556. DOI: 10.1109/43.476584  0.448
1995 Whitlock BK, Morikuni JJ, Conforti E, Kang S. Simulation and modeling: simulating optical interconnects Ieee Circuits & Devices. 11: 12-18. DOI: 10.1109/101.385721  0.354
1994 Diaz CH, Kang S, Duvvury C. Circuit-level electrothermal simulation of electrical overstress failures in advanced MOS I/O protection devices Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 13: 482-493. DOI: 10.1109/43.275358  0.395
1994 Diaz CH, Kang S, Duvvury C. Simulation of electrical overstress thermal failures in integrated circuits Ieee Transactions On Electron Devices. 41: 359-366. DOI: 10.1109/16.275221  0.379
1994 Díaz CH, Duvvury C, Kang S. Studies of EOS susceptibility in 0.6 μm nMOS ESD I/O protection structures Journal of Electrostatics. 33: 273-289. DOI: 10.1016/0304-3886(94)90035-3  0.316
1993 Sapatnekar SS, Rao VB, Vaidya PM, Kang S. An exact solution to the transistor sizing problem for CMOS circuits using convex optimization Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 12: 1621-1634. DOI: 10.1109/43.248073  0.378
1993 Díaz C, Kang S, Duvvury C, Wagner L. Electrical overstress (EOS) power profiles: A guideline to qualify EOS hardness of semiconductor devices Journal of Electrostatics. 31: 161-176. DOI: 10.1016/0304-3886(93)90007-T  0.383
1990 Gee P, Wu MY, Kang SM, Hajj IN. A metal-metal matrix cell generator for multi-level metal MOS technology Integration, the Vlsi Journal. 9: 25-47. DOI: 10.1016/0167-9260(90)90004-K  0.306
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