Thomas D. Burd, Ph.D.
Affiliations: | 2001 | University of California, Berkeley, Berkeley, CA, United States |
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Parents
Sign in to add mentor| Robert W. Brodersen | grad student | 2001 | UC Berkeley | |
| (Energy -efficient processor system design.) | ||||
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Publications
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| Munger B, Akeson D, Arekapudi S, et al. (2015) Carrizo: A High Performance, Energy Efficient 28 nm APU Ieee Journal of Solid-State Circuits |
| Kosonocky S, Burd T, Kasprak K, et al. (2012) Designing in scaled technologies: 32 nm and beyond Digest of Technical Papers - Symposium On Vlsi Technology. 147-148 |
| Burd TD, Pering TA, Stratakos AJ, et al. (2000) Dynamic voltage scaled microprocessor system Ieee Journal of Solid-State Circuits. 35: 1571-1580 |
| Burd TD, Brodersen RW. (2000) Design issues for Dynamic Voltage Scaling Proceedings of the International Symposium On Low Power Electronics and Design. 9-14 |
| Pering T, Burd T, Brodersen R. (2000) Voltage scheduling in the IpARM microprocessor system Proceedings of the International Symposium On Low Power Electronics and Design. 96-101 |
| Burd T, Pering T, Stratakos A, et al. (2000) A dynamic voltage scaled microprocessor system Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 294-295 |
| Pering T, Burd T, Brodersen R. (1998) Simulation and evaluation of dynamic voltage scaling algorithms Proceedings of the International Symposium On Low Power Design. 76-81 |
| Burd TD, Brodersen RW. (1996) Processor design for portable systems Journal of Vlsi Signal Processing Systems For Signal, Image, and Video Technology. 13: 203-221 |