Thomas D. Burd, Ph.D. - Publications

Affiliations: 
2001 University of California, Berkeley, Berkeley, CA, United States 

8 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2015 Munger B, Akeson D, Arekapudi S, Burd T, Fair HR, Farrell J, Johnson D, Krishnan G, McIntyre H, McLellan E, Naffziger S, Schreiber R, Sundaram S, White J, Wilcox K. Carrizo: A High Performance, Energy Efficient 28 nm APU Ieee Journal of Solid-State Circuits. DOI: 10.1109/JSSC.2015.2464688  0.446
2012 Kosonocky S, Burd T, Kasprak K, Schultz R, Stephany R. Designing in scaled technologies: 32 nm and beyond Digest of Technical Papers - Symposium On Vlsi Technology. 147-148. DOI: 10.1109/VLSIT.2012.6242504  0.31
2000 Burd TD, Pering TA, Stratakos AJ, Brodersen RW. Dynamic voltage scaled microprocessor system Ieee Journal of Solid-State Circuits. 35: 1571-1580. DOI: 10.1109/4.881202  0.32
2000 Burd TD, Brodersen RW. Design issues for Dynamic Voltage Scaling Proceedings of the International Symposium On Low Power Electronics and Design. 9-14.  0.485
2000 Pering T, Burd T, Brodersen R. Voltage scheduling in the IpARM microprocessor system Proceedings of the International Symposium On Low Power Electronics and Design. 96-101.  0.539
2000 Burd T, Pering T, Stratakos A, Brodersen R. A dynamic voltage scaled microprocessor system Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 294-295.  0.443
1998 Pering T, Burd T, Brodersen R. Simulation and evaluation of dynamic voltage scaling algorithms Proceedings of the International Symposium On Low Power Design. 76-81.  0.338
1996 Burd TD, Brodersen RW. Processor design for portable systems Journal of Vlsi Signal Processing Systems For Signal, Image, and Video Technology. 13: 203-221.  0.318
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