Year |
Citation |
Score |
2020 |
Bhat G, Tran N, Shill H, Ogras UY. w-HAR: An Activity Recognition Dataset and Framework Using Low-Power Wearable Devices. Sensors (Basel, Switzerland). 20. PMID 32962046 DOI: 10.3390/S20185356 |
0.321 |
|
2020 |
Tuncel Y, An S, Bhat G, Raja N, Lee HG, Ogras U. Voltage-Frequency Domain Optimization for Energy-Neutral Wearable Health Devices. Sensors (Basel, Switzerland). 20. PMID 32937970 DOI: 10.3390/s20185255 |
0.354 |
|
2020 |
Park J, Bhat G, Nk A, Geyik CS, Ogras UY, Lee HG. Optimization for Energy-Harvesting Wearable IoT Devices. Sensors (Basel, Switzerland). 20. PMID 32019219 DOI: 10.3390/S20030764 |
0.395 |
|
2020 |
Mandal SK, Bhat G, Doppa JR, Pande PP, Ogras ÜY. An Energy-aware Online Learning Framework for Resource Management in Heterogeneous Platforms Acm Transactions On Design Automation of Electronic Systems. 25: 1-26. DOI: 10.1145/3386359 |
0.317 |
|
2020 |
Bhat G, Gumussoy S, Ogras UY. Analysis and Control of Power-Temperature Dynamics in Heterogeneous Multiprocessors Ieee Transactions On Control Systems and Technology. 1-13. DOI: 10.1109/Tcst.2020.2974421 |
0.372 |
|
2020 |
Arda SE, Krishnakumar A, Goksoy AA, Kumbhare N, Mack J, Sartor AL, Akoglu A, Marculescu R, Ogras UY. DS3: A System-Level D omain- S pecific S ystem-on-Chip S imulation Framework Ieee Transactions On Computers. 69: 1248-1262. DOI: 10.1109/Tc.2020.2986963 |
0.442 |
|
2020 |
Krishnan G, Mandal SK, Chakrabarti C, Seo Js, Ogras UY, Cao Y. Interconnect-Aware Area and Energy Optimization for In-Memory Acceleration of DNNs Ieee Design & Test of Computers. 1-1. DOI: 10.1109/Mdat.2020.3001559 |
0.325 |
|
2020 |
Pasricha S, Ayoub R, Kishinevsky M, Mandal SK, Ogras UY. A Survey on Energy Management for Mobile and IoT Devices Ieee Design & Test of Computers. 1-1. DOI: 10.1109/Mdat.2020.2976669 |
0.307 |
|
2020 |
Sartor AL, Krishnakumar A, Arda SE, Ogras UY, Marculescu R. HiLITE: Hi erarchical and L ightweight I mita t ion L e arning for Power Management of Embedded SoCs Ieee Computer Architecture Letters. 19: 63-67. DOI: 10.1109/Lca.2020.2992182 |
0.398 |
|
2019 |
Charles S, Ahmed A, Ogras UY, Mishra P. Efficient Cache Reconfiguration Using Machine Learning in NoC-Based Many-Core CMPs Acm Transactions On Design Automation of Electronic Systems. 24: 60. DOI: 10.1145/3350422 |
0.431 |
|
2019 |
Mandal SK, Bhat G, Patil CA, Doppa JR, Pande PP, Ogras UY. Dynamic Resource Management of Heterogeneous Mobile Platforms via Imitation Learning Ieee Transactions On Very Large Scale Integration Systems. 27: 2842-2854. DOI: 10.1109/Tvlsi.2019.2926106 |
0.433 |
|
2019 |
Bhat G, Deb R, Ogras UY. OpenHealth: Open-Source Platform for Wearable Health Monitoring Ieee Design & Test of Computers. 36: 27-34. DOI: 10.1109/Mdat.2019.2906110 |
0.312 |
|
2019 |
Gupta U, Mandal SK, Mao M, Chakrabarti C, Ogras UY. A Deep Q-Learning Approach for Dynamic Management of Heterogeneous Processors Ieee Computer Architecture Letters. 18: 14-17. DOI: 10.1109/Lca.2019.2892151 |
0.416 |
|
2018 |
Bhat G, Singla G, Unver AK, Ogras UY. Algorithmic Optimization of Thermal and Power Management for Heterogeneous Mobile Platforms Ieee Transactions On Very Large Scale Integration Systems. 26: 544-557. DOI: 10.1109/Tvlsi.2017.2770163 |
0.394 |
|
2018 |
Gupta U, Babu M, Ayoub R, Kishinevsky M, Paterna F, Gumussoy S, Ogras UY. An Online Learning Methodology for Performance Modeling of Graphics Processors Ieee Transactions On Computers. 67: 1677-1691. DOI: 10.1109/Tc.2018.2840710 |
0.405 |
|
2017 |
Park J, Joshi H, Lee HG, Kiaei S, Ogras UY. Flexible PV-cell Modeling for Energy Harvesting in Wearable IoT Applications Acm Transactions On Embedded Computing Systems. 16: 1-20. DOI: 10.1145/3126568 |
0.412 |
|
2017 |
Bhat G, Gumussoy S, Ogras UY. Power-Temperature Stability and Safety Analysis for Multiprocessor Systems Acm Transactions in Embedded Computing Systems. 16: 145. DOI: 10.1145/3126567 |
0.375 |
|
2017 |
Gupta U, Patil CA, Bhat G, Mishra P, Ogras UY. DyPO: Dynamic Pareto-Optimal Configuration Selection for Heterogeneous MpSoCs Acm Transactions in Embedded Computing Systems. 16: 123. DOI: 10.1145/3126530 |
0.394 |
|
2016 |
Gupta U, Jain S, Ogras UY. Can systems extend to polymer? SoP architecture design and challenges International System On Chip Conference. 2016: 203-208. DOI: 10.1109/SOCC.2015.7406946 |
0.307 |
|
2016 |
Bogdan P, Garg S, Ogras UY. Energy-efficient computing from systems-on-chip to micro-server and data centers 2015 6th International Green and Sustainable Computing Conference. DOI: 10.1109/IGCC.2015.7393686 |
0.358 |
|
2016 |
Gupta U, Korrapati S, Matturu N, Ogras UY. A generic energy optimization framework for heterogeneous platforms using scaling models Microprocessors and Microsystems. 40: 74-87. DOI: 10.1016/J.Micpro.2015.06.009 |
0.463 |
|
2015 |
Gupta U, Ogras UY. Constrained energy optimizationin heterogeneous platforms using generalized scaling models Ieee Computer Architecture Letters. 14: 21-25. DOI: 10.1109/Lca.2014.2326603 |
0.439 |
|
2013 |
Chen X, Xu Z, Kim H, Gratz P, Hu J, Kishinevsky M, Ogras U. In-network monitoring and control policy for DVFS of CMP networks-on-chip and last level caches Acm Transactions On Design Automation of Electronic Systems. 18: 1-21. DOI: 10.1145/2504905 |
0.462 |
|
2013 |
Chen X, Xu Z, Kim H, Gratz PV, Hu J, Kishinevsky M, Ogras U, Ayoub R. Dynamic voltage and frequency scaling for shared resources in multicore processor designs Proceedings - Design Automation Conference. DOI: 10.1145/2463209.2488874 |
0.392 |
|
2013 |
Ogras UY, Marculescu R. Analysis and optimization of prediction-based flow control in networks-on-chip Lecture Notes in Electrical Engineering. 184: 105-133. DOI: 10.1145/1297666.1297677 |
0.358 |
|
2012 |
Ogras UY, Emre Y, Xu J, Kam T, Kishinevsky M. Energy-guided exploration of on-chip network design for exa-scale computing International Workshop On System Level Interconnect Prediction, Slip. 24-31. DOI: 10.1145/2347655.2347669 |
0.38 |
|
2012 |
Chatterjee S, Kishinevsky M, Ogras UY. xMAS: Quick Formal Modeling of Communication Fabrics to Enable Verification Ieee Design & Test of Computers. 29: 80-88. DOI: 10.1109/Mdt.2012.2205998 |
0.331 |
|
2011 |
David R, Bogdan P, Marculescu R, Ogras U. Dynamic power management of voltage-frequency island partitioned networks-on-chip using intel's sing-chip cloud computer Nocs 2011: the 5th Acm/Ieee International Symposium On Networks-On-Chip. 257-258. DOI: 10.1145/1999946.1999989 |
0.401 |
|
2011 |
Chou CL, Marculescu R, Ogras U, Chatterjee S, Kishinevsky M, Loukianov D. System interconnect design exploration for embedded MPSoCs International Workshop On System Level Interconnect Prediction, Slip. DOI: 10.1109/SLIP.2011.6135433 |
0.373 |
|
2011 |
Ayoub R, Ogras U, Gorbatov E, Jin Y, Kam T, Diefenbaugh P, Rosing T. OS-level power minimization under tight performance constraints in general purpose systems Proceedings of the International Symposium On Low Power Electronics and Design. 321-326. DOI: 10.1109/ISLPED.2011.5993657 |
0.331 |
|
2010 |
Ogras UY, Bogdan P, Marculescu R. An analytical approach for network-on-chip performance analysis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 2001-2013. DOI: 10.1109/Tcad.2010.2061613 |
0.443 |
|
2009 |
Ogras UY, Marculescu R, Marculescu D, Jung EG. Design and management of voltage-frequency island partitioned networks-on-chip Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 17: 330-341. DOI: 10.1109/Tvlsi.2008.2011229 |
0.651 |
|
2009 |
Marculescu R, Ogras UY, Peh LS, Jerger NE, Hoskote Y. Outstanding research problems in NoC design: System, microarchitecture, and circuit perspectives Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 3-21. DOI: 10.1109/Tcad.2008.2010691 |
0.356 |
|
2009 |
Garg S, Marculescu D, Marculescu R, Ogras U. Technology-driven limits on DVFS controllability of multiple voltage-frequency island designs: A system-level perspective Proceedings - Design Automation Conference. 818-821. |
0.575 |
|
2008 |
Zamora NH, Hu X, Ogras UY, Marculescu R. Enabling multimedia using resource-constrained video processing techniques: A node-centric perspective Acm Transactions On Design Automation of Electronic Systems. 13. DOI: 10.1145/1297666.1297684 |
0.375 |
|
2008 |
Chou CL, Ogras UY, Marculescu R. Energy- and performance-aware incremental mapping for networks on chip with multiple voltage levels Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 1866-1879. DOI: 10.1109/Tcad.2008.2003301 |
0.431 |
|
2008 |
Ogras UY, Marculescu R, Marculescu D. Variation-adaptive feedback control for networks-on-chip with multiple clock domains Proceedings - Design Automation Conference. 614-619. DOI: 10.1109/DAC.2008.4555891 |
0.59 |
|
2007 |
Lee HG, Chang N, Ogras UY, Marculescu R. On-chip communication architecture exploration: A quantitative evaluation of point-to-point, bus, and network-on-chip approaches Acm Transactions On Design Automation of Electronic Systems. 12. DOI: 10.1145/1255456.1255460 |
0.465 |
|
2007 |
Grecu C, Ivanov A, Pande P, Jantsch A, Salminen E, Ogras U, Marculescu R. Towards open network-on-chip benchmarks Proceedings - Nocs 2007: First International Symposium On Networks-On-Chip. 205-212. DOI: 10.1109/NOCS.2007.44 |
0.311 |
|
2007 |
Ogras UY, Marculescu R, Lee HG, Choudhary P, Marculescu D, Kaufman M, Nelson P. Challenges and promising results in NoC prototyping using FPGAs Ieee Micro. 27: 86-95. DOI: 10.1109/Mm.2007.80 |
0.605 |
|
2007 |
Ogras UY, Marculescu R, Choudhary P, Marculescu D. Voltage-frequency island partitioning for GALS-based networks-on-chip Proceedings - Design Automation Conference. 110-115. DOI: 10.1109/DAC.2007.375135 |
0.633 |
|
2006 |
Lee HG, Ogras UY, Marculescu R, Chang N. Design space exploration and prototyping for on-chip multimedia applications Proceedings - Design Automation Conference. 137-142. DOI: 10.1145/1146909.1146949 |
0.369 |
|
2006 |
Marculescu R, Ogras UY, Zamora NH. Computation and communication refinement for multiprocessor SoC design: A system-level perspective Acm Transactions On Design Automation of Electronic Systems. 11: 564-592. DOI: 10.1145/1142980.1142983 |
0.333 |
|
2006 |
Hu J, Ogras UY, Marculescu R. System-level buffer allocation for application-specific networks-on-chip router design Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 2919-2933. DOI: 10.1109/Tcad.2006.882474 |
0.432 |
|
2005 |
Ogras UY, Marculescu R. Energy- and performance-driven NoC communication architecture synthesis using a decomposition approach Proceedings -Design, Automation and Test in Europe, Date '05. 352-357. DOI: 10.1109/DATE.2005.137 |
0.33 |
|
2004 |
Hu X, Ogras UY, Zamora NH, Marculescu R. Data partitioning techniques for pervasive multimedia platforms 2004 Ieee International Conference On Multimedia and Expo (Icme). 2: 1035-1038. |
0.332 |
|
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